28F004/400B3, 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
2. Since each column lists specifications for a different V and V
voltage range combination, the test
CCQ
CC
conditions V Max, V
Max, V Min, and V
Min refer to the maximum or minimum V or V
CC
CCQ
CC
CCQ CC CCQ
voltage listed at the top of each column. V Max is 3.3 V on 0.25µm 32-Mbit devices.
CC
3. Automatic Power Savings (APS) reduces I
4. Sampled, not 100% tested.
to approximately standby levels in static operation.
CCR
5. Erase and program are inhibited when V < V
and not guaranteed outside the valid V ranges of
PP
PP
PPLK
V
, V
V
and V
For read operations or during idle time, a 5 V supply may be applied to V
PP1
PP2, PP3
P
P
4
.
P
P
indefinitely. However, V must be at valid levels for program and erase operations.
PP
6. Applying V = 11.4 V–12.6 V during program/erase can only be done for a maximum of 1000 cycles on the
PP
main blocks and 2500 cycles on the parameter blocks. V may be connected to 12 V for a total of 80 hours
PP
maximum. See Section 3.4 for details. For read operations or during idle time, a 5 V supply may be applied to
V
indefinitely. However, V must be at valid levels for program and erase operations.
PP
PP
Figure 5. Input/Output Reference Waveform
VCCQ
VCCQ
VCCQ
2
OUTPUT
INPUT
TEST POINTS
2
0.0
0580_05
NOTE: AC test inputs are driven at V
for a logic “1” and 0.0V for a logic “0.” Input timing begins, and output
CCQ
timing ends, at V
/2. Input rise and fall times (10%–90%) <10 ns. Worst case speed conditions are
CCQ
when V
= V
Min.
CCQ
CCQ
Figure 6. Test Configuration
V
CCQ
R
R
1
Device
under
Test
Out
CL
2
0580_06
NOTE: See table for component values.
Test Configuration Component Values for Worst
Case Speed Conditions
Test Configuration
CL (pF)
R1 (Ω)
R2 (Ω)
V
V
V
Standard Test
Standard Test
Standard Test
50
50
50
25 K
14.5 K
16 K
25 K
14.5 K
16 K
CCQ1
CCQ2
CCQ3
NOTE: C includes jig capacitance.
L
22
3UHOLPLQDU\
INTEL [ INTEL ]
