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Intel Advanced+ Boot Block Flash Memory (C3)
Table 19. Write Operations—32 Mbit Density
Density
Product
32 Mbit
70 ns
90 ns
100 ns
110 ns
100
#
Sym
Parameter
3.0 V – 3.6 V6
2.7 V – 3.6 V
Note
90
Unit
V
CC
70
90
100
Min
110
Min
Min
Min
Min
Min
tPHWL
tPHEL
/
RP# High Recovery to WE# (CE#)
Going Low
W1
W2
4,5
4,5
150
0
150
0
150
150
0
150
150
0
ns
ns
tELWL
tWLEL
/
CE# (WE#) Setup to WE# (CE#)
Going Low
0
0
tWLWH
/
W3
WE# (CE#) Pulse Width
1,4,5
45
60
60
70
70
70
ns
tELEH
tDVWH
tDVEH
/
/
/
/
/
W4
W5
W6
W7
W8
W9
W10
Data Setup to WE# (CE#) Going High
2,4,5
2,4,5
4,5
40
50
0
40
60
0
50
60
0
60
70
0
60
70
0
60
70
0
ns
ns
ns
ns
ns
ns
tAVWH
tAVEH
Address Setup to WE# (CE#) Going
High
tWHEH
tEHWH
CE# (WE#) Hold Time from WE#
(CE#) High
tWHDX
tEHDX
Data Hold Time from WE# (CE#)
High
2,4,5
2,4,5
1,4,5
0
0
0
0
0
0
tWHAX
tEHAX
Address Hold Time from WE# (CE#)
High
0
0
0
0
0
0
tWHWL /
tEHEL
WE# (CE#) Pulse Width High
25
30
30
30
30
30
tVPWH
tVPEH
/
VPP Setup to WE# (CE#) Going High
VPP Hold from Valid SRD
3,4,5
3,4
200
0
200
0
200
0
200
0
200
0
200
0
ns
ns
ns
W11 tQVVL
tBHWH
W12
/
WP# Setup to WE# (CE#) Going
High
3,4
0
0
0
0
0
0
tBHEH
W13 tQVBL
W14 tWHGL
NOTES:
WP# Hold from Valid SRD
3,4
3,4
0
0
0
0
0
0
ns
ns
WE# High to OE# Going Low
30
30
30
30
30
30
1. Write pulse width (tWP) is defined from CE# or WE# going low (whichever goes low last) to CE# or WE# going high (whichever
goes high first). Hence, tWP = tWLWH = tELEH = tWLEH = tELWH. Similarly, write pulse width high (tWPH) is defined from CE# or
WE# going high (whichever goes high first) to CE# or WE# going low (whichever goes low last). Hence,
t
WPH = tWHWL = tEHEL = tWHEL = tEHWL.
2. Refer to Table 7, “Command Bus Operations” on page 24 for valid AIN or DIN
3. Sampled, but not 100% tested.
.
4. See Figure 11, “AC Input/Output Reference Waveform” on page 49 for timing measurements and maximum allowable input
slew rate.
5. See Figure 9, “Write Operations Waveform” on page 47.
6. VCCMax = 3.3 V for 32-Mbit 0.25 Micron product.
Datasheet
45
INTEL [ INTEL ]
