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Intel Advanced+ Boot Block Flash Memory (C3)
Table 20. Write Operations—64Mbit Density
Density
64 Mbit
80 ns
Min
#
Sym
Parameter
Product
Unit
V
2.7 V – 3.6 V Note
CC
tPHWL
tPHEL
/
W1
W2
W3
W4
W5
W6
W7
W8
W9
W10
RP# High Recovery to WE# (CE#) Going Low
CE# (WE#) Setup to WE# (CE#) Going Low
WE# (CE#) Pulse Width
4,5
4,5
150
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
tELWL
tWLEL
/
tWLWH
tELEH
/
1,4,5
2,4,5
2,4,5
4,5
60
40
60
0
tDVWH
tDVEH
/
Data Setup to WE# (CE#) Going High
Address Setup to WE# (CE#) Going High
CE# (WE#) Hold Time from WE# (CE#) High
Data Hold Time from WE# (CE#) High
Address Hold Time from WE# (CE#) High
WE# (CE#) Pulse Width High
tAVWH
tAVEH
/
tWHEH
tEHWH
/
/
/
tWHDX
tEHDX
2,4,5
2,4,5
1,4,5
0
tWHAX
tEHAX
0
tWHWL /
tEHEL
30
tVPWH
tVPEH
/
VPP Setup to WE# (CE#) Going High
VPP Hold from Valid SRD
3,4,5
3,4
200
0
ns
ns
ns
W11 tQVVL
tBHWH
W12
/
WP# Setup to WE# (CE#) Going High
3,4
0
tBHEH
W13 tQVBL
W14 tWHGL
NOTES:
WP# Hold from Valid SRD
3,4
3,4
0
ns
ns
WE# High to OE# Going Low
30
1. Write pulse width (tWP) is defined from CE# or WE# going low (whichever goes low last) to CE# or
WE# going high (whichever goes high first). Hence, tWP = tWLWH = tELEH = tWLEH = tELWH
.
Similarly, write pulse width high (tWPH) is defined from CE# or WE# going high (whichever goes
high first) to CE# or WE# going low (whichever goes low last). Hence,
t
WPH = tWHWL = tEHEL = tWHEL = tEHWL.
2. Refer to Table 7, “Command Bus Operations” on page 24 for valid AIN or DIN
3. Sampled, but not 100% tested.
.
4. See Figure 11, “AC Input/Output Reference Waveform” on page 49 for timing measurements and
maximum allowable input slew rate.
5. See Figure 9, “Write Operations Waveform” on page 47.
46
Datasheet
INTEL [ INTEL ]
