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Intel Advanced+ Boot Block Flash Memory (C3)
Table 16. Read Operations — 64 Mbit Density
Density
Product
64 Mbit
70 ns
2.7 V–3.6 V
80 ns
#
Sym
Parameter
Unit
V
2.7 V–3.6 V
CC
Note
Min
Max
Min
Max
R1
R2
R3
R4
R5
R6
R7
R8
R9
tAVAV Read Cycle Time
3,4
3,4
70
80
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAVQV Address to Output Delay
tELQV CE# to Output Delay
tGLQV OE# to Output Delay
tPHQV RP# to Output Delay
tELQX CE# to Output in Low Z
tGLQX OE# to Output in Low Z
tEHQZ CE# to Output in High Z
tGHQZ OE# to Output in High Z
70
70
80
80
1,3,4
1,3,4
3,4
20
20
150
150
2,3,4
2,3,4
2,3,4
2,3,4
0
0
0
0
20
20
20
20
Output Hold from Address, CE#, or OE#
Change, Whichever Occurs First
R10
tOH
2,3,4
0
0
ns
NOTES:
1. OE# may be delayed up to tELQV– GLQV
2. Sampled, but not 100% tested.
3. See Figure 8, “Read Operation Waveform” on page 42.
t
after the falling edge of CE# without impact on tELQV.
4. See Figure 11, “AC Input/Output Reference Waveform” on page 49 for timing measurements and
maximum allowable input slew rate.
Figure 8. Read Operation Waveform
R1
R2
R3
Address [A]
CE# [E]
R8
R4
R9
OE# [G]
WE# [W]
R7
R6
R10
Data [D/Q]
RST# [P]
R5
42
Datasheet
INTEL [ INTEL ]
