256-Mbit J3 (x8/x16)
0606_16
NOTES:
1. CE low is defined as the last edge of CE0, CE1, or CE2 that enables the device. CE high is defined at the
X
X
first edge of CE0, CE1, or CE2 that disables the device (see Table 13).
2. When reading the flash array a faster t
(R16) applies. For non-array reads, R4 applies (i.e.: Status
GLQV
Register reads, query reads, or device identifier reads).
Figure 10. 4-Word Page Mode Read Waveform
R1
R2
A[MAX:3] [A]
A[2:1] [A]
00
01
10
11
R3
CEx [E]
R4
OE# [G]
WE# [W]
R8
R10
R9
R6
R7
R10
R15
D[15:0] [Q]
RP# [P]
1
2
3
4
R5
NOTE: CE low is defined as the last edge of CE0, CE1, or CE2 that enables the device. CE high is defined at
X
X
the first edge of CE0, CE1, or CE2 that disables the device (see Table 13).
24
Datasheet
INTEL [ INTEL ]
