256-Mbit J3 (x8/x16)
7.2
Write Operations
Table 9. Write Operations
Valid for All
Speeds
Versions
Unit
Notes
#
Symbol
(t
Parameter
RP# High Recovery to WE# (CE ) Going Low
Min
Max
W1
W2
t
t
t
t
t
t
t
t
t
t
t
t
t
)
1
0
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1,2,3
1,2,4
1,2,4
1,2,5
1,2,5
1,2,
PHWL PHEL
X
(t
)
CE (WE#) Low to WE# (CE ) Going Low
ELWL WLEL
X
X
W3
Write Pulse Width
70
50
55
0
WP
W4
(t
)
Data Setup to WE# (CE ) Going High
X
DVWH DVEH
W5
(t
)
Address Setup to WE# (CE ) Going High
X
AVWH AVEH
W6
(t
)
CE (WE#) Hold from WE# (CE ) High
X X
WHEH EHWH
W7
(t
)
Data Hold from WE# (CE ) High
0
1,2,
WHDX EHDX
X
W8
(t
)
Address Hold from WE# (CE ) High
0
1,2,
WHAX EHAX
X
W9
Write Pulse Width High
30
0
1,2,6
1,2,3
1,2,7
1,2,8
1,2,3,8,9
WPH
W11
W12
W13
W15
(t
)
V
Setup to WE# (CE ) Going High
PEN X
VPWH VPEH
(t
)
Write Recovery before Read
WE# (CE ) High to STS Going Low
35
WHGL EHGL
(t
)
500
WHRL EHRL
X
V
Hold from Valid SRD, STS Going High
PEN
0
QVVL
NOTES:
CE low is defined as the first edge of CE0, CE1, or CE2 that enables the device. CE high is defined at the first edge of CE0, CE1,
X
X
or CE2 that disables the device (see Table 13).
1. Read timing characteristics during block erase, program, and lock-bit configuration operations are the same as
during read-only operations. Refer to AC Characteristics–Read-Only Operations.
2. A write operation can be initiated and terminated with either CE or WE#.
X
3. Sampled, not 100% tested.
4. Write pulse width (t ) is defined from CE or WE# going low (whichever goes low last) to CE or WE# going
WP
X
X
high (whichever goes high first). Hence, t
= t
= t
= t
= t
.
WP
WLWH
ELEH
WLEH
ELWH
5. Refer to Table 14 for valid A and D for block erase, program, or lock-bit configuration.
IN
IN
6. Write pulse width high (t
) is defined from CE or WE# going high (whichever goes high first) to CE or WE#
WPH
X
X
going low (whichever goes low first). Hence, t
= t
= t
= t
= t
.
WPH
WHWL
EHEL
WHEL
EHWL
7. For array access, t
is required in addition to t
for any accesses after a write.
AVQV
WHGL
8. STS timings are based on STS configured in its RY/BY# default mode.
9. V should be held at V until determination of block erase, program, or lock-bit configuration success
PEN
PENH
(SR[1,3,4:5] = 0).
26
Datasheet
INTEL [ INTEL ]
