E
BYTE-WIDE SMART 5 FlashFile™ MEMORY FAMILY
Commercial Temperature DC Characteristics for
4-, 8-, and 16-Mbit Smart 5 FlashFile™ Memories (Continued)
5.0V VCC Test
Notes Min Max Unit Conditions
Sym
Parameter
VIL
Input Low Voltage
7
–0.5
0.8
V
V
VIH
Input High Voltage
7
2.0
VCC
+ 0.5
VOL
Output Low Voltage
3,7
3,7
3,7
0.45
V
V
V
V
VCC = VCC Min
IOL = 5.8 mA
VOH1 Output High Voltage
(TTL)
2.4
VCC = VCC Min
IOH = –2.5 mA
VOH2 Output High Voltage
(CMOS)
0.85
VCC
VCC = VCC Min
IOH = –2.5 mA
VCC
–0.4
VCC = VCC Min
IOH = –100 µA
VPPLK VPP Lockout Voltage
VPPH1 VPP Voltage
4,7
8,9
1.5
5.5
V
V
V
V
V
4.5
11.4
2.0
VPPH2 VPP Voltage
12.6
VLKO VCC Lockout Voltage
VHH
RP# Unlock Voltage
11.4
12.6
Set Master Lock-Bit
Override Lock-Bit
NOTES:
1. All currents are in RMS unless otherwise noted. Typical values at nominalVCC voltage and TA = +25°C. These currents are
valid for all product versions (packages and speeds).
2.
I
CCWS and ICCES are specified with the device de-selected. If read or written while in erase suspend mode, the device’s
current is the sum of ICCWS or ICCES and ICCR or ICCW
3. Includes RY/BY#.
.
4. Block erases, programs, and lock-bit configurations are inhibited when VPP ≤ VPPLK, and not guaranteed in the range
between VPPLK (max) and VPPH1 (min), between VPPH1 (max) and VPPH2 (min), and above VPPH2 (max).
5. Automatic Power Savings (APS) reduces typical ICCR to 1 mA in static operation.
6. CMOS inputs are either VCC ± 0.2V or GND ± 0.2V. TTL inputs are either VIL or VIH
.
7. Sampled, not 100% tested.
8. Master lock-bit set operations are inhibited when RP# = V . Block lock-bit configuration operations are inhibited when the
IH
master lock-bit is set and RP# = VIH. Block erases and programs are inhibited when the corresponding block-lock bit is set
and RP# = VIH. Block erase, program, and lock-bit configuration operations are not guaranteed and should not be
attempted with VIH < RP# < VHH
.
9. RP# connection to a VHH supply is allowed for a maximum cumulative period of 80 hours.
29
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