BYTE-WIDE SMART 5 FlashFile™ MEMORY FAMILY
E
6.2.6
COMMERCIAL TEMPERATURE AC CHARACTERISTICS - WRITE OPERATIONS(1,2)
Commercial Temperature Write Operations for
4-, 8-, and 16-Mbit Smart 5 FlashFile™ Memories at TA = 0°C to +70°C
5V ± 5%,
5V ± 10% VCC
Valid for All
Speeds
Versions(4)
Unit
#
W1 tPHWL (tPHEL
W2 tELWL (tWLEL
W3 tWP
W4 tDVWH (tDVEH
W5 tAVWH (tAVEH
W6 tWHEH (tEHWH
W7 tWHDX (tEHDX
W8 tWHAX (tEHAX
W9 tWPH
W10 tPHHWH (tPHHEH
W11 tVPWH (tVPEH
W12 tWHGL (tEHGL
Sym
Parameter
Notes Min Max
)
RP# High Recovery to WE# (CE#) Going Low
CE# (WE#) Setup to WE# (CE#) Going Low
Write Pulse Width
3
7
7
4
4
1
0
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
)
50
40
40
0
)
Data Setup to WE# (CE#) Going High
Address Setup to WE# (CE#) Going High
CE# (WE#) Hold from WE# (CE#) High
Data Hold from WE# (CE#) High
)
)
)
5
)
Address Hold from WE# (CE#) High
Write Pulse Width High
5
8
3
3
25
100
100
0
)
RP# VHH Setup to WE# (CE#) Going High
VPP Setup to WE# (CE#) Going High
Write Recovery before Read
)
)
W13 tWHRL (tEHRL
)
WE# (CE#) High to RY/BY# Going Low
RP# VHH Hold from Valid SRD, RY/BY# High
VPP Hold from Valid SRD, RY/BY# High
90
W14 tQVPH
3,5
3,5
0
0
W15 tQVVL
NOTES:
1. Read timing characteristics during block erase, program, and lock-bit configuration operations are the same as during
read-only operations. Refer to AC Characteristics for read-only operations.
2. A write operation can be initiated and terminated with either CE# or WE#.
3. Sampled, not 100% tested.
4. Refer to Table 3 for valid AIN and DIN for block erase, program, or lock-bit configuration.
5.
V
PP should be held at VPPH1/2 (and if necessary RP# should be held at VHH) until determination of block erase, program, or
lock-bit configuration success (SR.1/3/4/5 = 0).
6. See Ordering Information for device speeds (valid operational combinations).
7. Write pulse width (tWP) is defined from CE# or WE# going low (whichever goes low last) to CE# or WE# going high
(whichever goes high first). Hence, tWP = tWLWH = tELEH = tWLEH = tELWH. If CE# is driven low 10 ns before WE# going low,
WE# pulse width requirement decreases to tWP - 20 ns.
8. Write pulse width high (tWPH) is defined from CE# or WE# going high (whichever goes high first) to CE# or WE# going low
(whichever goes low last). Hence, tWPH = tWHWL = tEHEL = tWHEL = tEHWL
.
32
PRODUCT PREVIEW
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