E
BYTE-WIDE SMART 5 FlashFile™ MEMORY FAMILY
5.4 Trace on Printed Circuit
5.0 DESIGN CONSIDERATIONS
V
PP
Boards
5.1
Three-Line Output Control
Updating flash memories that reside in the target
system requires that the printed circuit board
designer pay attention to the VPP power supply
trace. The VPP pin supplies the memory cell current
for byte writing and block erasing. Use similar trace
widths and layout considerations given to the VCC
power bus. Adequate VPP supply traces and
decoupling will decrease VPP voltage spikes and
overshoots.
Intel provides three control inputs to accommodate
multiple memory connections: CE#, OE#, and RP#.
Three-line control provides for:
a. Lowest possible memory power dissipation.
b. Data bus contention avoidance.
To use these control inputs efficiently, an address
decoder should enable CE# while OE# should be
connected to all memory devices and the system’s
READ# control line. This assures that only selected
memory devices have active outputs while de-
selected memory devices are in standby mode.
RP# should be connected to the system
POWERGOOD signal to prevent unintended writes
during system power transitions. POWERGOOD
should also toggle during system reset.
5.5
V
, V , RP# Transitions
CC PP
Block erase, program and lock-bit configuration are
not guaranteed if VPP or VCC fall outside of a valid
voltage
range
(VCC1/2
and
VPPH1/2
)
or
RP# ≠ VIH or VHH. If V error is detected, status
register bit SR.3 is setPtPo “1” along with SR.4 or
SR.5, depending on the attempted operation. If RP#
transitions to VIL during block erase, program, or
lock-bit configuration, RY/BY# will remain low until
the reset operation is complete. Then, the operation
will abort and the device will enter deep power-
down. The aborted operation may leave data
partially altered. Therefore, the command sequence
must be repeated after normal operation is
restored.
5.2
RY/BY# Hardware Detection
RY/BY# is a full CMOS output that provides a
hardware method of detecting block erase, program
and lock-bit configuration completion. This output
can be directly connected to an interrupt input of
the system CPU. RY/BY# transitions low when the
WSM is busy and returns to VOH when it is finished
executing the internal algorithm. During suspend
and deep power-down modes, RY/BY# remains at
5.6
Power-Up/Down Protection
VOH
.
The device is designed to offer protection against
accidental block erasure, byte writing, or lock-bit
configuration during power transitions. Upon power-
up, the device is indifferent as to which power
5.3
Power Supply Decoupling
supply (VPP or VCC) powers-up first. Internal
Flash memory power switching characteristics
require careful device decoupling. System
designers are interested in three supply current
issues: standby current levels, active current levels
and transient peaks produced by falling and rising
edges of CE# and OE#. Two-line control and proper
decoupling capacitor selection will suppress
transient voltage peaks. Each device should have a
0.1 µF ceramic capacitor connected between its
VCC and GND and between its VPP and GND.
These high-frequency, low-inductance capacitors
should be placed as close as possible to package
leads. Additionally, for every eight devices, a 4.7 µF
electrolytic capacitor should be placed at the array’s
power supply connection between VCC and GND.
The bulk capacitor will overcome voltage slumps
caused by PC board trace inductance.
circuitry resets the CUI to read array mode at
power-up.
A system designer must guard against spurious
writes for VCC voltages above VLKO when VPP is
active. Since both WE# and CE# must be low for a
command write, driving either input signal to VIH will
inhibit writes. The CUI’s two-step command
sequence architecture provides an added level of
protection against data alteration.
In-system block lock and unlock renders additional
protection during power-up by prohibiting block
erase and program operations. The device is
disabled while RP# = VIL regardless of its control
inputs state.
25
PRODUCT PREVIEW
INTEL [ INTEL ]
