ISA-to-PC-Card (PCMCIA) Controllers — PD6710/’22
Figure 29. DMA Write Cycle Timing
IRQ10
(DRQ)
IRQ9
(DACK*)
t
1
-IOWR, -WE
(high)
-REG
(DACK* to card)
-CE[2:1]
t
t
2
4
t
3
-IORD
-WAIT
t
t
6
5
DMA DATA[15:0]
to card
t
7
-VPP_VALID
(TC from system)
t
t
9
8
-OE
(TC to card)
t
t
t
12
10
11
DMA DATA[15:0]
from card
Table 38. DMA Request Timing (PD6722 only)
Symbol
Parameter
MIN
MAX
Units
t
DMA request from socket interface to system1
40
ns
1
1. After FIFO empty, DMA requests held off from being presented to the system until all write data to a card has been emptied
from the socket interface FIFO.
Datasheet
119
INTEL [ INTEL ]
