ISA-to-PC-Card (PCMCIA) Controllers — PD6710/’22
Table 26. ISA Bus Timing (Sheet 2 of 2)
Symbol
Parameter
IOCS16* inactive delay from SA[15:0]1
MIN
MAX
Unit
t
40
ns
2a
SA[16:0], SBHE* setup to any Command active1, 2
LA[23:17] latching by ALE to any Command active
30
90
ns
ns
t
3
4
t
Any Command active to IOCHRDY inactive (low)3
IOCHRDY three-state from Command inactive4
MEMCS16* inactive delay from unlatched LA[23:17]
IOW* or IOR* pulse width1
40
30
40
ns
t
5
4a
t
ns
ns
ns
ns
ns
5
t
140
180
100
0
6a
6b
t
MEMW* or MEMR* pulse width1
t
Any Command inactive to next Command active
7
8
t
Address or SBHE* hold from any Command inactive
Data valid from MEMW* active5
Data valid from IOW* active
40
40
ns
ns
t
9
Data hold from MEMW* inactive
Data hold from IOW* inactive
5
5
ns
ns
t
10
t
Data delay from IOR* active, for internal registers
Data delay from IOCHRDY active
0
130
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
11
12
13
14
15
16
17
18
19
20
t
t
t
t
t
t
t
t
t
Data hold from IOR* or MEMR* inactive
AEN inactive setup to valid IOR* or IOW* active
AEN hold from IOR* or IOW* inactive
0
40
5
30
REFRESH* inactive setup to valid MEMR* or MEMW* active
REFRESH* inactive hold from MEMR* or MEMW* active
MEMCS16* active delay from SA[16:12] valid
*ZWS delay from MEMW* active
40
0
40
30
15
*ZWS hold from MEMW* inactive
1. AEN must be inactive for t , t , and t timing specifications to be applicable.
2
3
6
2. Command is defined as IOR*, IOW*, MEMR*, or MEMW*.
3. Except for valid card memory writes, which are zero wait state when internal write FIFO is not full.
4. If card is removed during a card access cycle, IOCHRDY is three-stated without waiting for end of Command.
5. Based on 25-MHz internal clock, produced either by an internal synthesizer and 14.318-MHz signal applied to CLK pin, or by
supplying 25 MHz directly to CLK pin and bypassing the internal synthesizer.
Datasheet
105
INTEL [ INTEL ]
