3 Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family
7.3
Noise Reduction
Stacked-CSP memory’s power switching characteristics require careful device decoupling. System
designers should consider three supply current issues for both the flash and SRAM:
1. Standby current levels (ICCS
2. Read current levels (ICCR
)
)
3. Transient peaks produced by falling and rising edges of F-CE#, S-CS1#, and S-CS2.
Transient current magnitudes depend on the device outputs’ capacitive and inductive loading. Two-
line control and proper decoupling capacitor selection will suppress these transient voltage peaks.
Each device should have a capacitors between individual power (F-VCC, F-VCCQ, F-VPP
S-VCC) and ground (GND) signals. High-frequency, inherently low-inductance capacitors,should
be placed as close as possible to the package leads.
Noise issues within a system can cause devices to operate erratically if it is not adequately filtered.
In order to avoid any noise interaction issues within a system, it is recommended that the design
contain the appropriate number of decoupling capacitors in the system. Noise issues can also be
reduced if leads to the device are kept very short, in order to reduce inductance.
Decoupling capacitors between VCC and VSS reduce voltage spikes by supplying the extra current
needed during switching. Placing these capacitors as close to the device as possible reduces line
inductance. The capacitors should be low inductance capacitors; surface mount capacitors typically
exhibit lower inductance.
It is highly recommended that systems use a 0.1 µf capacitor for each of the D9, D10, A10 and E4
grid ballout locations (see Figure 1, “66-Ball Stacked Chip Scale Package” on page 8 for ballout).
These capacitors are necessary to avoid undesired conditions created by excess noise. Smaller
capacitors can be used to decouple higher frequencies.
Datasheet
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INTEL [ INTEL ]
