3 Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family
7.4.1
7.4.2
SRAM Operation during Flash “Busy”
This functionality provides the ability to use both the flash and the SRAM “at the same time”
within a system, similar to the operation of two devices with separate footprints. This operation can
be achieved by following the appropriate timing constraints within a system.
Simultaneous Bus Operations
Operations that require both the SRAM and Flash to be in active mode are disallowed. An example
of these cases would include simultaneous reads on both the flash and SRAM, which would result
in contention for the data bus. Finally, a read of one device while attempting to write to the other
(similar to the conditions of direct memory access (DMA) operation) are also not within the
recommended operating conditions. Basically, only one memory can drive the outputs out the
device at one given point in time.
7.5
Printed Circuit Board Notes
The Intel Stacked-CSP will save significant space on your PCB by combining two chips into one
BGA style package. Intel Stacked-CSP has a 0.8 mm pitch that can be routed on your Printed
Circuit Board with conventional design rules. Trace widths of 0.127 mm (0.005 inches) are typical.
Unused balls in the center of the package are not populated to further increase the routing options.
Standard surface mount process and equipment can be used for the Intel Stacked-CSP.
Figure 14. Standard PCB Design Rules Can be Used with Stacked-CSP Device
Land Pad Diameter: 0.35 mm (0.0138 in)
Solder Mask Opening: 0.50 mm (0.0198 in)
Trace Width: 0.127 mm (0.005 in)
Trace Spaces: 0.160 mm (0.00625 in)
Via Capture Pad: 0.51 mm (0.020 in)
Via Drill Size: 0.25 mm (0.010 in)
NOTE: Top View
7.6
System Design Notes Summary
The Advanced+ Boot Block Stacked-CSP allows higher levels of memory component integration.
Different power supply configurations can be used within the system to achieve different
objectives. At least three different 0.1 µf capacitors should be used to decouple the devices within a
system. SRAM reads or writes during a flash program or erase are supported operations. Standard
printed circuit board technology can be used.
Datasheet
45
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