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RD38F1010C0ZTL0 参数 Datasheet PDF下载

RD38F1010C0ZTL0图片预览
型号: RD38F1010C0ZTL0
PDF下载: 下载PDF文件 查看货源
内容描述: 3 VOLT英特尔?高级+引导?座闪存?记忆? ( C3) ?堆叠芯片? ScalPackage ? Familye [3 VOLT INTEL Advanced+BootBlock FlashMemory(C3)Stacked-ChipScalPackageFamilye]
分类和应用: 闪存
文件页数/大小: 70 页 / 1167 K
品牌: INTEL [ INTEL ]
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3 Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family  
7.2.1  
F-RP# Connected to System Reset  
The use of F-RP# during system reset is important with automated program/erase devices since the  
system expects to read from the flash memory when it comes out of reset. If a CPU reset occurs  
without a flash memory reset, proper CPU initialization will not occur because the flash memory  
may be providing status information instead of array data. Intel recommends connecting F-RP# to  
the system CPU RESET# signal to allow proper CPU/flash initialization following system reset.  
System designers must guard against spurious writes when F-VCC voltages are above VLKO. Since  
both F-WE# and F-CE# must be low for a command write, driving either signal to VIH will inhibit  
writes to the device. The CUI architecture provides additional protection since alteration of  
memory contents can only occur after successful completion of the two-step command sequences.  
The device is also disabled until F-RP# is brought to VIH, regardless of the state of its control  
inputs.  
By holding the device in reset (F-RP# connected to system PowerGood) during power-up/down,  
invalid bus conditions during power-up can be masked, providing yet another level of memory  
protection.  
7.2.2  
F-VCC, F-VPP and F-RP# Transition  
The CUI latches commands as issued by system software and is not altered by F-VPP or F-CE#  
transitions or WSM actions. Its default state upon power-up, after exit from reset mode or after  
F-VCC transitions above VLKO (Lockout voltage), is read array mode.  
After any program or block erase operation is complete (even after F-VPP transitions down to  
VPPLK), the CUI must be reset to read array mode via the Read Array command if access to the  
flash memory array is desired.  
Figure 12. Example Power Supply Configurations  
System Supply  
System Supply  
VCC  
VPP  
VCC  
12 V Supply  
VPP  
Prot#  
(Logic Signal)  
10  
KΩ  
12 V Fast Programming  
Low-Voltage Programming  
Absolute Write Protection With V PP  
VPPLK  
Absolute Write Protection via Logic Signal  
System Supply  
(Note 1)  
System Supply  
VCC  
VCC  
VPP  
VPP  
12 V Supply  
Low Voltage and 12 V Fast Programming  
Low-Voltage Programming  
NOTE: 1. A resistor can be used if the F-V supply can sink adequate current based on resistor value.  
CC  
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Datasheet  
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