3 Volt Intel® Advanced+ Boot Block Flash Memory Stacked-CSP Family
Figure 13. Typical Flash + SRAM Substrate Power and Ground Connections
SUBSTRATE
FLASH DIE
SRAM DIE
S-VSSQ
A9
D9
F-VSSQ
S-VCC
S-VCCQ
D3
S-VSS
F-VCC
D10
A10
F-VCCQ
E4
F-VPP
F-VSS
H8
XX
Substrate connection to package ball
S-X
F-X
SRAM die bond pad connection
Flash die bond pad connection
NOTES:
1. Substrate connections refer to ballout locations shown in Figure 1, “66-Ball Stacked Chip Scale Package” on
page 8.
2. 0.1µf capacitors should be used with D9, D10, A10and E4.
3. Some SRAM devices do not have a S-VSSQ; in this case, this pad is a S-VSS.
4. Some SRAM devices do not have a S-VSSQ; in this case, this pad is a VCC.
7.4
Simultaneous Operation
The term simultaneous operation in used to describe the ability to read or write to the SRAM while
also programming or erasing flash. In addition, F-CE#, S-CS1# and S-CS2 should not be enabled at
the same time. (See Table 2, “3 Volt Intel® Advanced+ Boot Block Stacked-CSP Ball
Descriptions” on page 9 for a summary of recommended operating modes.) Simultaneous
operation of the can be summarized by the following:
• SRAM read/write are during a Flash Program or Erase Operation are allowed.
• Simultaneous Bus Operations between the Flash and SRAM are not allowed (because of bus
contention).
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Datasheet
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