28F640L30, 28F128L30, 28F256L30
Figure 16. Synchronous Single-Word Array or Non-array Read Timing
Latency Count
R301
R306
CLK [C]
R2
Address [A]
R101
R104
R106
R105
ADV# [V]
R303
R102
R3
R8
CE# [E]
OE# [G]
WAIT [T]
R7
R9
R15
R307
R304
R17
R312
R4
R305
Data [D/Q]
NOTES:
1. WAIT is driven per OE# assertion during synchronous array or non-array read, and can be configured to
assert either during or one data cycle before valid data.
2. This diagram illustrates the case in which an n-word burst is initiated to the flash memory array and it is
terminated by CE# deassertion after the first word in the burst.
Figure 17. Continuous Burst Read, showing an Output Delay Timing
R301
R302
R306
R304
R304
R304
CLK [C]
Address [A]
ADV# [V]
R2
R101
R106
R105
R303
R102
R3
CE# [E]
OE# [G]
R15
R307
R304
R312
WAIT [T]
R4
R7
R305
R305
R305
R305
Data [D/Q]
58
Datasheet
INTEL [ INTEL ]
