28F640L30, 28F128L30, 28F256L30
NOTE: At the end of Word Line; the delay incurred when a burst access crosses a 16-word boundary and the
starting address is not 4-word boundary aligned.
Figure 18. Synchronous Burst-Mode Four-Word Read Timing
Latency Count
R302
R301
R306
CLK [C]
Address [A]
ADV# [V]
R2
R101
A
R105
R102
R106
R303
R3
R8
CE# [E]
OE# [G]
WAIT [T]
R9
R15
R17
R307
R4
R304
R305
Q0
R7
R304
R10
Data [D/Q]
Q1
Q2
Q3
NOTE: WAIT is driven per OE# assertion during synchronous array or non-array read. WAIT asserted during
initial latency and deasserted during valid data (CR.10 = 0 Wait asserted low).
Figure 19. Burst Suspend Timing
R304
R305
R305
CLK
R1
R2
Ad dre ss [A]
R101
R105
R106
ADV#
CE# [E]
OE# [G]
R3
R4
R9
R4
R15
R312
R17
R15
WAIT [T]
WE# [W]
R7
R6
R304
Q1
R304
Q2
DATA [D/Q]
Q0
Q1
NOTES:
1. CLK can be stopped in either high or low state.
2. WAIT is driven per OE# assertion during synchronous array or non-array read. WAIT asserted during initial
latency and deasserted during valid data (CR.10 = 0 Wait asserted low).
Datasheet
59
INTEL [ INTEL ]
