28F640L30, 28F128L30, 28F256L30
12.0
AC Characteristics
12.1
AC Read Specifications (VCCQ = 2.2 V – 3.3 V)
Speed
–85
Max
–110
Num
Symbol
Parameter
Units Notes
Min
Min
Max
Asynchronous Specifications
R1
R2
R3
R4
R5
R6
R7
R8
R9
tAVAV
tAVQV
tELQV
tGLQV
tPHQV
tELQX
tGLQX
tEHQZ
tGHQZ
Read cycle time
85
110
ns
Address to output valid
85
85
110
110
30
ns
ns
ns
ns
ns
ns
ns
ns
6
CE# low to output valid
OE# low to output valid
RST# high to output valid
CE# low to output in low-Z
OE# low to output in low-Z
CE# high to output in high-Z
OE# high to output in high-Z
25
1,2
1
150
150
0
0
0
0
1,3
1,2,3
24
24
24
24
1,3
Output hold from first occurring address, CE#, or OE#
change
R10
tOH
0
0
ns
R11
R12
R13
R15
R16
R17
tEHEL
tELTV
tEHTZ
tGLTV
tGLTX
tGHTZ
CE# pulse width high
20
20
ns
ns
ns
ns
ns
ns
1
1
CE# low to WAIT valid
CE# high to WAIT high Z
OE# low to WAIT valid
OE# low to WAIT in low-Z
OE# high to WAIT in high-Z
16
17
17
20
20
20
1,3
1
0
0
1,3
1,3
20
24
Latching Specifications
R101
R102
R103
R104
R105
R106
R108
R111
tAVVH
tELVH
tVLQV
tVLVH
tVHVL
tVHAX
Address setup to ADV# high
CE# low to ADV# high
ADV# low to output valid
ADV# pulse width low
10
10
12
12
ns
ns
ns
ns
ns
ns
ns
ns
85
25
110
25
1
10
10
9
12
12
10
ADV# pulse width high
Address hold from ADV# high
Page address access
1,4
1
t
APA
t
RST# high to ADV# high
30
30
1
phvh
Clock Specifications
R200
R201
R202
R203
fCLK
tCLK
CLK frequency
CLK period
52
3
40
3
MHz
ns
19.2
9
25
9
1,3
tCH/CL
CLK high/low time
ns
tFCLK/RCLK CLK fall/rise time
ns
Synchronous Specifications
R301
R302
R303
tAVCH/L
tVLCH/L
tELCH/L
Address setup to CLK
ADV# low setup to CLK
CE# low setup to CLK
9
9
9
9
9
9
ns
ns
ns
ns
ns
ns
ns
1
R304 tCHQV / tCLQV CLK to output valid
17
20
20
22
R305
R306
R307
tCHQX
tCHAX
tCHTV
Output hold from CLK
Address hold from CLK
CLK to WAIT valid
3
3
1,5
1,4,5
1,5
10
10
Datasheet
55
INTEL [ INTEL ]
