28F640L30, 28F128L30, 28F256L30
Figure 22. Write to Asynchronous Read Timing
W5
W8
R1
Address [A]
ADV# [V]
W2
W6
R10
CE# [E}
W3
W18
WE# [W]
W14
OE# [G]
R15
R17
WAIT [T]
R4
R2
R3
R8
W4
W7
R9
Data [D/Q]
RST# [P]
D
Q
W1
Figure 23. Synchronous Read to Write Timing
Latency Count
R302
R301
R306
CLK [C]
Address [A]
ADV# [V]
R2
W5
R101
W18
R105
R102
R106
R104
W20
R303
R11
R13
R3
W6
CE# [E]
OE# [G]
R4
R8
W19
W9
W8
W15
W2
W3
WE#
WAIT [T]
R16
R307
R304
R312
R7
R305
W7
Data [D/Q]
Q
D
D
NOTE: WAIT shown de-asserted and High-Z per OE# de-assertion during write operation (CR[10]=0 Wait
asserted low). Clock is ignored during write operation.
62
Datasheet