28F640L30, 28F128L30, 28F256L30
Speed
–85
Max
–110
Num
Symbol
Parameter
Units Notes
Min
Min
Max
R311
tCHVL
tCHTX
CLK Valid to ADV# Setup
WAIT Hold from CLK
0
0
ns
ns
1
R312
3
3
1,5
NOTES:
1. See Figure 26, “AC Input/Output Reference Waveform” on page 65 for timing measurements and maximum
allowable input slew rate.
2. OE# may be delayed by up to t
3. Sampled, not 100% tested.
– t
after CE#’s falling edge without impact to t
.
ELQV
GLQV
ELQV
4. Address hold in synchronous burst mode is t
or t
, whichever timing specification is satisfied first.
CHAX
VHAX
5. Applies only to subsequent synchronous reads.
l
Figure 13. Asynchronous Single-Word Read (ADV# Low)
R1
R2
Ad dre ss [A]
ADV#
R3
R8
CE# [E}
R4
R9
OE# [G]
R15
R17
WAIT [T]
R7
R6
Data [D/Q]
R5
RST# [P]
NOTE: WAIT shown de-asserted during asynchronous read mode (CR[10]=0 Wait asserted low).
56
Datasheet
INTEL [ INTEL ]
