Fast Ethernet 10/100 Hex Transceiver with Full MII — LXT9763
1.2
Interface Descriptions
Figure 3. LXT9763 Interfaces
TX_CLKn
TXDn_<3:0>
TX_ENn
TPFOPn
TPFONn
MII
Data
I/F
TX_ERn
Network
I/F
RX_CLKn
RXDn_<3:0>
RX_DVn
RX_ERn
COLn
TPFIPn
TPFINn
CRSn
MDIO
MDC
MII
Mgmt
I/F
MDINT
ADD<4:0>
RBIAS
VCCIO
Hardware
Control I/F
& Port LEDs
LED/CFGn_1
LED/CFGn_2
LED/CFGn_3
22.1k
+3.3V
+3.3V
VCCD
GNDD
.01uF
1.2.1
10/100 Network Interface
The LXT9763 supports both 10BASE-T and 100BASE-TX Ethernet over twisted-pair, or 100
Mbps Ethernet over fiber media (100BASE-FX). Each of the six network interface ports consists of
four external pins (two differential signal pairs). The pins are shared between twisted-pair (TP) and
fiber. Refer to Table 2 on page 13 for specific pin assignments.
The LXT9763 output drivers generate either 100BASE-TX, 10BASE-T, or 100BASE-FX output.
When not transmitting data, the LXT9763 generates 802.3-compliant link pulses or idle code. Input
signals are decoded either as a 100BASE-TX, 100-BASE-FX, or 10BASE-T input, depending on
the mode selected. Auto-negotiation/parallel detection or manual control is used to determine the
speed of this interface.
1.2.2
Twisted-Pair Interface
When operating at 100 Mbps, the LXT9763 continuously transmits and receives MLT3 symbols.
When not transmitting data, the LXT9763 generates “IDLE” symbols.
During 10 Mbps operation, Manchester-encoded data is exchanged. When no data is being
exchanged, the line is left in an idle state.
The LXT9763 supports either 100BASE-TX or 10BASE-T connections over 100Ω, Category 5,
Unshielded Twisted Pair (UTP) cable. Only a transformer, RJ-45 connector, series capacitors and
load resistor, and bypass capacitors are required to complete this interface. On the receive side, the
Datasheet
17
INTEL [ INTEL ]
