LXT9763 — Fast Ethernet 10/100 Hex Transceiver with Full MII
internal impedance is high enough that it has no practical effect on the external termination circuit.
On the transmit side, Intel’s patented waveshaping technology shapes the outgoing signal to help
reduce the need for external EMI filters. Four slew rate settings (refer to Table 3 on page 13) allow
the designer to match the output waveform to the magnetic characteristics.
1.2.3
Fiber Interface
The LXT9763 provides a PECL interface that complies with the ANSI X3.166 specification. This
interface is suitable for driving a fiber-optic coupler. Fiber ports cannot be enabled via auto-
negotiation; they must be enabled via the MDIO interface.
1.2.4
1.2.5
Configuration Management Interface
The LXT9763 provides both an MDIO interface and a hardware control interface (via the LED/
CFG pins) for device configuration and management.
MDIO Management Interface
The LXT9763 supports the IEEE 802.3 MII Management Interface also known as the Management
Data Input/Output (MDIO) Interface. This interface allows upper-layer devices to monitor and
control the state of the LXT9763. The MDIO interface consists of a physical connection, a specific
protocol that runs across the connection, and an internal set of addressable registers.
Some registers are required and their functions are defined by the IEEE 802.3 specification. The
LXT9763 also supports additional registers for expanded functionality. The LXT9763 supports 12
internal registers per port (48 total), each of which is 16 bits wide. Specific register bits are
referenced using an “X.Y” notation, where X is the register number (0-32) and Y is the bit number
(0-15).
The physical interface consists of a data line (MDIO) and clock line (MDC). The timing for the
MDIO Interface is shown in Table 33 on page 57. MDIO read and write cycles are shown in Figure
5 (read) and Figure 6 (write).
1.3
MII Addressing
The protocol allows one controller to communicate with multiple LXT9763 chips. Pins
ADD_<4:0> determine the base address. Each port adds its port number to the base address to
obtain its port address as shown in Figure 4.
18
Datasheet
INTEL [ INTEL ]
