LXT9763 — Fast Ethernet 10/100 Hex Transceiver with Full MII
Table 3. LXT9763 Miscellaneous Signal Descriptions (Continued)
Pin#
Symbol
Type1
Signal Description2
Address <4:0>. Sets base address. Each port adds its port number to this
address to determine its PHY address.
101
100
99
98
97
ADD_4
I
I
I
I
I
Port 0 Address = Base + 0.
Port 1 Address = Base + 1.
Port 2 Address = Base + 2.
Port 3 Address = Base + 3.
Port 4 Address = Base + 4.
Port 5 Address = Base + 5.
ADD_3
ADD_2
ADD_1
ADD_0
Bias. This pin provides bias current for the internal circuitry. Must be tied to
ground through a 22.1 kΩ, 1% resistor.
102
RBIAS
I
92
REFCLK
N/C
I
Reference Clock. A 25 MHz clock is required at this pin.
No Connection. These pins should be left floating.
127-134
-
1. Type Column Coding: I = Input, O = Output, A = Analog.
2. The LXT9763 supports the 802.3 MDIO register set. Specific bits in the registers are referenced using an “X.Y” notation,
where X is the register number (0-32) and Y is the bit number (0-15).
Table 4. LXT9763 Power Supply Signal Descriptions
Pin#
Symbol
Type
Signal Description
107, 114, 123, 138, 147, 154
106, 115, 122, 139, 146, 155
VCCT
VCCR
-
-
Transmitter Supply. +3.3V supply for analog circuits.
Receiver Supply. +3.3V supply for analog circuits.
Digital Power Supply - Core. +3.3V supply for core digital
circuits.
80, 89, 179
VCCD
VCCIO
GNDD
-
-
-
Digital Power Supply - I/O Ring. 3.3V supply for digital
15, 31, 52, 67, 193, 208
I/O circuits. Regardless of the IO supply, digital I/O pins remain
tolerant of 5V signal levels.
1, 16, 32, 53, 68, 81, 87, 88, 178,
192
Digital Ground. Ground return for both core and I/O digital
supplies (VCCD and VCCIO).
103, 110, 111, 118, 119, 126, 135,
142, 143, 150, 151, 158
GNDA
GNDS
-
-
Analog Ground. Ground return for analog supply.
Substrate Ground. Ground for chip substrate.
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Table 5. LXT9763 JTAG Test Signal Descriptions
Pin#
Symbol
Type1
Signal Description
163
164
165
166
167
TDI
I / IP
O
Test Data Input. Test data sampled with respect to the rising edge of TCK.
Test Data Output. Test data driven with respect to the falling edge of TCK.
Test Mode Select.
TDO
TMS
TCK
I / IP
I / ID
I / IP
Test Clock. Clock for JTAG test (REFCLK).
TRST
Test Reset. Reset input for JTAG test.
1. Type Column Coding: I = Input, O = Output, A = Analog, IP = weak internal pull-up, ID = weak internal pull-down.
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Datasheet
INTEL [ INTEL ]
