Fast Ethernet 10/100 Quad Transceivers — LXT974/LXT975
Figure 8. Management Interface - Read Frame Structure
MDC
MDIO
(Read)
D1
D0
A4
A3
A0
R4
R3
R0
D15 D14
D14 D1
D15
Z
0
32 "1"s
0
1
1
0
Turn
Around
Data
Read
Idle
Idle
Preamble
SFD
Op Code
PHY Address
Register Address
Write
Figure 9. Management Interface - Write Frame Structure
MDC
MDIO
(Write)
A4
A3
A0
R4
R3
R0
D15
D14
D1
D0
32 "1"s
0
1
0
1
0
1
Turn
Around
Idle
Preamble
SFD
Op Code
PHY Address
Register Address
Data
Idle
Write
MII Interrupts
The LXT974/975 provides interrupt signals in two ways. The MDIO interrupt reflects the interrupt
status of each port addressed by the read. Details are shown in Figure 10.
Setting bit 17.1 = 1 on all four ports, enables global interrupts using the MDINT pin. An active
Low on this pin indicates a status change on the LXT974/975. Interrupts may be caused by:
• Link status change
• Auto-negotiation complete
• Full-duplex status change
• Jabber detect
Figure 10. MDIO Interrupt Signaling
MDC
INT
MDIO
Interrupt
MDIO FRAME
0
Z
Turn
Around
Read Data
Sourced by PHY
Idle
2.2.3
Hardware Control Interface
The Hardware Control Interface is used to configure operating characteristics of the LXT974/975.
When MDDIS is Low, this interface provides initial values for the MDIO registers, and then
passes control to the MDIO Interface. When MDDIS is High, this interface provides continuous
control over the LXT974/975.
Datasheet
25
INTEL [ INTEL ]
