LXT974/LXT975 — Fast Ethernet 10/100 Quad Transceivers
Individual chip addressing allows multiple LXT974/975 devices to share the MII in either mode.
Table 15 through Table 17 show how to set up the desired operating configurations using the
Hardware Control Interface.
Table 15. Configuring the LXT974/975 via Hardware Control
Desired Configuration
Pin Name
Input Value
MDIO Registers
AUTOENA
SD/TPn
High
Low
Low
High
Low
0.12 = 1
19.2 = 0
0.12 = 0
19.3 = 1
19.3 = 0
Auto-Negotiation Enabled on all ports1, 2, 3
Auto-Negotiation Disabled on all ports4
Scrambler Bypassed on all ports
AUTOENA
BYPSCR
BYPSCR
Scrambler Enabled on all ports
1. SD/TPn must be set Low for Auto-Negotiation operation.
2. Refer to Table 16 for Hardware Control Interface functions advertised when auto-negotiation is enabled.
3. Fiber operation can be forced per port via SD/TPn pins when auto-negotiation is enabled. See Table 17 for details.
4. Refer to Table 17 for Hardware Control Interface functions available when auto-negotiation is disabled.
Table 16. Configuring LXT974/975 Auto-Negotiation Advertisements Via
Hardware Control
Pin Settings
MDIO Registers
Desired
Configuration1,2
SD/TPn
(per port)
FDE
(global)
CFG_2
(global)
CFG_1
(global)
CFG_03
(global)
4.5
4.6
4.7
4.8
Advertise All
Low
Low
Low
Low
Low
Low
Ignore
Low
Low
High
High
Low
Low
High
Low
Low
Low
High
High
High
Ignore
Ignore
Ignore
Ignore
Ignore
Ignore
1
0
0
1
1
1
1
0
0
0
1
0
1
1
1
0
0
1
1
0
1
0
0
0
Advertise 100 HD
Advertise 100 HD/FD
Advertise 10 HD
High
Low
Advertise 10 HD/FD
Advertise 10/100 HD
High
Low
1. Refer to Table 15 for basic configurations.
2. Refer to Table 17 for Hardware Control Interface functions available when auto-negotiation is disabled.
3. Auto-Negotiation is not affected by CFG_0.
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Datasheet
INTEL [ INTEL ]
