LXT974/LXT975 — Fast Ethernet 10/100 Quad Transceivers
Figure 6. MII Data Interface
TX_CLKn
TX_ENn
TXD<3:0>n
TX_ERn
Media Access
Controller
LXT974/975
RX_CLKn
MAC
RX_DVn
RXD<3:0>n
RX_ERn
CRSn
COLn
Transmit Clock
The LXT974/975 is the master clock source for data transmission. The LXT974/975 automatically
sets the speed of TX_CLK to match port conditions. If the port is operating at 100 Mbps, TX_CLK
is set to 25 MHz. If the port is operating at 10 Mbps, TX_CLK is set to 2.5 MHz. The transmit data
and control signals must always be synchronized to TX_CLK by the MAC. The LXT974/975
normally samples these signals on the rising edge of TX_CLK.
However, Advanced TX_CLK Mode is available by setting MII register bit 19.5=1. In this mode,
the LXT974/975 samples the transmit data and control signals on the falling edge of TX_CLK.
When operating under MDIO Control, the user can advance the transmit clock relative to
TXD<3:0> and TX_ER. When Advance TX_CLK Mode is selected, the LXT974/975 clocks TXD
data in on the falling edge of TX_CLK, instead of the rising edge. This mode provides an increase
in timing margins of TXD, relative to TX_CLK. Advance TX_CLK Mode is enabled when bit 19.5
= 1.
Transmit Enable
The MAC must assert TX_EN the same time as the first nibble of preamble, and de-assert TX_EN
after the last bit of the packet.
Receive Data Valid
The LXT974/975 asserts RX_DV when it receives a valid packet. Timing changes depend on line
operating speed:
• For 100TX and 100FX links, RX_DV is asserted from the first nibble of preamble to the last
nibble of the data packet.
• For 10BT links, the entire preamble is truncated. RX_DV is asserted with the first nibble of
the Start of Frame Delimiter (SFD) “5D” and remains asserted until the end of the packet.
Error Signals
Whenever the LXT974/975 receives an errored symbol from the network, it asserts RX_ER and
drives “1110” on the RXD pins.
When the MAC asserts TX_ER, the LXT974/975 drives “H” symbols out on the line.
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Datasheet
INTEL [ INTEL ]
