LXT974/LXT975 — Fast Ethernet 10/100 Quad Transceivers
Figure 7. Loopback Paths
100FX
Loopback
10T
Loopback
FX
Driver
Digital
Block
Analog
Block
MII
TX
Driver
100TX
Loopback
Collision
The LXT974/975 asserts its collision signal, asynchronously to any clock, whenever the line state
is half-duplex and the transmitter and receiver are active at the same time. Table 14 summarizes the
conditions for assertion of carrier sense, collision, and data loopback signals.
Table 14. Carrier Sense, Loopback, and Collision Conditions
Speed & Duplex Condition
Carrier Sense
Loopback
Collision
Full-Duplex at 10 Mbps or 100 Mbps
100 Mbps, Half-Duplex
Receive Only
None
None
Yes
None
Transmit or Receive
Transmit or Receive
Transmit or Receive
Transmit and Receive
Transmit and Receive
Transmit and Receive
10 Mbps, Half-Duplex, 19.11 = 0
10 Mbps, Half-Duplex, 19.11 = 1
None
2.2.2.2
MII Management Interface
The LXT974/975 supports the IEEE 802.3 MII Management Interface also known as the
Management Data Input/Output (MDIO) Interface. This interface allows upper-layer devices to
monitor and control the state of the LXT974/975. The MDIO interface consists of a physical
connection, a specific protocol that runs across the connection, and an internal set of addressable
registers. Some registers are required and their functions are defined by the IEEE 802.3
specification. Additional registers are allowed for expanded functionality. The LXT974/975 is
configured with both sets of registers.
The physical interface consists of a data line (MDIO) and clock line (MDC). Operation of this
interface is controlled by the MDDIS input pin. When MDDIS is High, the MDIO operates as a
read-only interface. When MDDIS is Low, both read and write are enabled. The timing for the
MDIO Interface is shown in Table 40 on page 61. The protocol is shown in Figure 8 and Figure 9
(read and write). The protocol allows one controller to communicate with up to eight LXT974/975
chips. Bits A4:2 of the 5-bit PHY address are assigned as the LXT974/975 address. Bits A1:0 are
assigned as port addresses 0 through 3. The LXT974/975 supports 12 internal registers per port (48
total), each of which is 16 bits wide.
24
Datasheet
INTEL [ INTEL ]
