Fast Ethernet 10/100 Quad Transceivers — LXT974/LXT975
Only a transformer (1:1 on receive side, 2:1 on transmit side), load resistors, and bypass capacitors
are needed to complete this interface. Using Intel’s patented waveshaping technology, the
transmitter pre-distorts the outgoing signal to reduce the need for external filters for EMI
compliance.
A 4kΩ passive load is always present across the twisted-pair inputs. When enabled, the twisted-
pair inputs are actively biased to approximately 2.8V.
2.2.1.2
Fiber Interface
The LXT974/975 provides a PECL interface that complies with the ANSI X3.166 specification.
This interface is suitable for driving a fiber-optic coupler.
The twisted-pair pin assignments are remapped to support the PECL interface. The LXT974
supports both the twisted-pair and fiber interface on all four ports. The LXT975, optimized for TP
operation with dual-high RJ-45 connectors, provides dual interfaces on ports 1 and 3.
During 100BASE-FX operation, the FIBI pins receive differential PECL signals and the FIBO pins
produce differential PECL output signals.
Fiber ports cannot be enabled via auto-negotiation; they must be enabled via the Hardware Control
Interface or MDIO registers.
2.2.2
MII Interface
The LXT974/975 supports four standard MIIs (one per port). This interface consists of a data
interface and a management interface. The MII Data Interface passes data between the LXT974/
975 and one or more Media Access Controllers (MACs). Separate signals are provided for
transmit and receive. This interface operates at either 10 Mbps or 100 Mbps. The speed is set
automatically, once the operating conditions of the network link have been determined.
Nine signals are used to pass received data to the MAC: RXD<3:0>, RX_CLK, RX_DV, RX_ER,
COL and CRS. Seven signals are used to transmit data from the MAC: TXD<3:0>, TX_CLK,
TX_EN, and TX_ER.
2.2.2.1
MII Data Interface
Figure 6 shows the data portion of the MII interface. Separate channels are provided for
transmitting data from the MAC to the LXT974/975 (TXD), and for receiving data (RXD) from the
line.
Each channel has its own clock, data bus, and control signals. The LXT974/975 supplies both
clock signals as well as separate outputs for carrier sense and collision. Data transmission across
the MII is implemented in 4-bit-wide nibbles.
Tristating the MII
The LXT974/975 asserts RX_DV, RXD, RX_CLK and RX_ER as soon as it receives a packet from
the network. When TRSTEn is High, the associated port output signals are tristated.
Datasheet
21
INTEL [ INTEL ]
