Fast Ethernet 10/100 Quad Transceivers — LXT974/LXT975
Table 9. LXT974 and LXT975 Miscellaneous Signal Descriptions
Pin#
Symbol
Type1
Signal Description2
ADD1
ADD0
Port
0
0
1
1
0
1
0
1
0
1
2
3
20
19
18
ADD4
ADD3
ADD2
I
I
I
Address <4:2>. Set upper three bits of PHY
address. ADD<1:0> are set internally to match
port number as shown at right.
101, 112, 159
140
TEST
I
I
Test. Must be tied Low.
Bias. This pin provides bias current for the internal circuitry. Must be tied to
ground through a 22 kΩ resistor.
RBIAS
Clock Input. A 25 MHz clock input is required at this pin. Refer to Functional
Description for detailed clock requirements.
118
109
CLK25M
RESET
I
I
Reset. This active Low input is OR’ed with the control register Reset bit (0.15).
The LXT974/975 reset cycle is extended 205 µs (nominal) after Reset is de-
asserted.
Power Down. When High, forces LXT974/975 into power down mode. This pin is
OR’ed with the Power Down bit (0.11). Refer to Table 44 on page 64 for more
information.
102
PWRDN
N/C
I
41, 119, 120
-
No Connection. Leave open.
1. Type Column Coding: I = Input, O = Output, A = Analog.
2. The LXT974/975 supports the 802.3 MDIO register set. Specific bits in the registers are referenced using an “X.Y” notation,
where X is the register number (0-6 or 16-20) and Y is the bit number (0-15).
Table 10. LXT974 and LXT975 LED Indicator Signal Descriptions
Pin#2
Symbol
Type1
Signal Description3
11
8
4
LED0_0
LED1_0
LED2_0
LED3_0
LED0 - Ports 0 - 3. In default mode, active Low output indicates transmitter active. However,
LED0 is programmable and may also be set to indicate receiver active, link status or duplex
status. Refer to LED Configuration Register, Table 51 on page 68, for details on
programming options.
OD
1
12
9
5
LED0_1
LED1_1
LED2_1
LED3_1
LED1 - Ports 0 - 3. In default mode, active Low output indicates receiver active. However,
LED1 is programmable and may also be set to indicate link status, duplex status, or operating
speed. Refer to LED Configuration Register, Table 51 on page 68, for details on
programming options.
OD
OD
2
13
10
6
LED0_2
LED1_2
LED2_2
LED3_2
LED2 - Ports 0 - 3. In default mode, active Low output indicates link up. However, LED2 is
programmable and may also be set to indicate duplex status, operating speed or collision.
Refer to LED Configuration Register, Table 51 on page 68, for details on
programming options.
3
17
15
16
LEDENA
LEDCLK
LEDDAT
O
O
O
LED Enable. Active High output signals external device that LEDDAT is active.
LED Clock. 25 MHz clock for LED serial data output.
LED Data. Serial data output for 24 LEDs (6 x 4 ports) data.
1. Type Column Coding: I = Input, O = Output, OD = Open Drain.
2. Unused pins should be tied Low.
3. The LXT974/975 supports the 802.3 MDIO register set. Specific bits in the registers are referenced using an “X.Y” notation,
where X is the register number (0-6 or 16-20) and Y is the bit number (0-15).
Datasheet
17
INTEL [ INTEL ]
