LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
Figure 10. 10BASE-T Clocking
2.5 MHz during auto-negotiation and 10BASE-T Data & Idle
TX_CLK
(Sourced by LXT971A)
2.5 MHz during auto-negotiation and 10BASE-T Data & Idle
RX_CLK
(Sourced by LXT971A)
Constant 25 MHz
XI
Figure 11. 100BASE-X Clocking
2.5 MHz during auto-negotiation
25 MHz once 100BASE-X
Link Established
TX_CLK
(Sourced by LXT971A)
2.5 MHz during auto-negotiation
25 MHz once 100BASE-X
Link Established
RX_CLK
(Sourced by LXT971A)
Constant 25 MHz
XI
Figure 12. Link Down Clock Transition
Link-Down Condition/Auto-Negotiate Enabled
RX_CLK
TX_CLK
Any Clock
2.5 MHz Clock
Clock transition time will not exceed
2X the nominal clock period:
10 Mbps = 2.5 MHz
100 Mbps = 25 MHz
3.6.7
Loopback
The LXT971A provides two loopback functions, operational and test (see
Loopback
paths are shown in
34
Datasheet
Document #: 249414
Revision #: 002
Rev. Date: August 7, 2002
INTEL [ INTEL CORPORATION ]
