LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
Figure 15. 100BASE-TX Data Path
Standard Data Flow
+1
Parallel
D0
to
0
0
0
Serial
D1
Scramble
-1
4B/5B
MLT3
D0 D1 D2 D3
S0 S1 S2 S3 S4
De-
D2
D3
Transition = 1.
Serial
to
Scramble
No Transition = 0.
All transitions must follow
Parallel
pattern: 0, +1, 0, -1, 0, +1...
Scrambler Bypass Data Flow
S0
+1
Parallel
to
S1
0
0
0
Serial
-1
MLT3
S2
S0 S1 S2 S3 S4
Transition = 1.
Serial
S3
to
No Transition = 0.
All transitions must follow
Parallel
S4
pattern: 0, +1, 0, -1, 0, +1...
As shown in Figure 14 on page 36, the MAC starts each transmission with a preamble pattern. As
soon as the LXT971A detects the start of preamble, it transmits a Start-of-Stream Delimiter (SSD,
symbols J and K) to the network. It then encodes and transmits the rest of the packet, including the
balance of the preamble, the SFD, packet data, and CRC.
Once the packet ends, the LXT971A transmits the End-of- Stream Delimiter (ESD, symbols T and
R) and then returns to transmitting Idle symbols. 4B/5B coding is shown in Table 11 on page 40.
Figure 16 shows normal reception with no errors. When the LXT971A receives invalid symbols
from the line, it asserts RX_ER as shown in Figure 17.
Figure 16. 100BASE-TX Reception with No Errors
RX_CLK
RX_DV
preamble SFD SFD DA DA DA DA
CRC
CRC
CRC
CRC
RXD<3:0>
RX_ER
Figure 17. 100BASE-TX Reception with Invalid Symbol
RX_CLK
RX_DV
preamble SFD SFD DA DA XX XX XX XX XX XX XX XX XX XX
RXD<3:0>
RX_ER
Datasheet
37
Document #: 249414
Revision #: 002
Rev. Date: August 7, 2002
INTEL [ INTEL ]
