T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation — LXT351
Table 26. Master and Transmit Clock Timing Characteristics for T1 Operation
(See Figure 14)
Parameter
Sym
Min
Typ1
Max
Unit
Notes
Master clock frequency
MCLK
MCLKt
MCLKd
TCLK
TCLKt
TCLKd
tSUT
–
–
1.544
–
–
MHz
ppm
%
must be supplied
Master clock tolerance
±32
Master clock duty cycle
40
–
–
60
–
Transmit clock frequency
Transmit clock tolerance
Transmit clock duty cycle
TPOS/TNEG to TCLK setup time
TCLK to TPOS/TNEG hold time
1.544
MHz
ppm
%
–
–
–
–
–
±100
90
–
10
50
50
ns
tHT
–
ns
1. Typical figures are at 25° C and are for design aid only; not guaranteed and not subject to production testing.
Table 27. Master and Transmit Clock Timing Characteristics for E1 Operation
(See Figure 14)
Parameter
Sym
Min
Typ1
Max
Unit
Notes
Master clock frequency
MCLK
MCLKt
MCLKd
TCLK
TCLKt
TCLKd
tSUT
–
–
2.048
–
–
MHz
ppm
%
must be supplied
Master clock tolerance
±32
Master clock duty cycle
40
–
–
60
–
Transmit clock frequency
Transmit clock tolerance
Transmit clock duty cycle
TPOS/TNEG to TCLK setup time
TCLK to TPOS/TNEG hold time
2.048
MHz
ppm
%
–
–
–
–
–
±100
90
–
10
50
50
ns
tHT
–
ns
1. Typical figures are at 25° C and are for design aid only; not guaranteed and not subject to production testing.
Figure 14. Transmit Clock Timing
Datasheet
37
INTEL [ INTEL ]
