LXT351 — T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation
Table 28. Receive Timing Characteristics for T1 Operation (See Figure 15)
Parameter
Receive clock duty cycle 2, 3
Sym
Min
Typ1
Max
Unit
RLCKd
tPW
40
–
50
60
–
%
ns
ns
ns
ns
ns
Receive clock pulse width 2, 3
648
324
324
274
274
Receive clock pulse width High
Receive clock pulse width Low1,3
RPOS/RNEG to RCLK rise time
RCLK rise to RPOS/RNEG hold time
tPWH
tPWL
tSUR
tHR
–
–
260
–
388
–
–
–
1. Typical s are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
2. RCLK duty cycle widths will vary according to extent of received pulse jitter displacement. Max and Min RCLK duty cycles
are for worst case jitter conditions.
3. Worst case conditions guaranteed by design only.
Table 29. Receive Timing Characteristics for E1 Operation (See Figure 15)
Parameter
Receive clock duty cycle 2, 3
Sym
Min
Typ1
Max
Unit
RLCKd
tPW
40
–
50
60
–
%
ns
ns
ns
ns
ns
Receive clock pulse width 2, 3
488
244
244
194
194
Receive clock pulse width High
Receive clock pulse width Low1,3
RPOS/RNEG to RCLK rise time
RCLK rise to RPOS/RNEG hold time
tPWH
tPWL
tSUR
tHR
–
–
195
–
293
–
–
–
1. Typical figures are at 25 °C and are for design aid only; not guaranteed and not subject to production testing.
2. RCLK duty cycle widths will vary according to extent of received pulse jitter displacement. Max and Min. RCLK duty cycles
are for worst case jitter conditions (0.4 UI clock displacement for 1.544 MHz).
3. Worst case conditions guaranteed by design only.
Figure 15. Receive Clock Timing
38
Datasheet
INTEL [ INTEL ]
