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LXT351QE 参数 Datasheet PDF下载

LXT351QE图片预览
型号: LXT351QE
PDF下载: 下载PDF文件 查看货源
内容描述: PCM收发器|单| CEPT PCM - 30 / E - 1 | CMOS | QFP | 44PIN |塑料\n [PCM TRANSCEIVER|SINGLE|CEPT PCM-30/E-1|CMOS|QFP|44PIN|PLASTIC ]
分类和应用: 电信集成电路PC
文件页数/大小: 46 页 / 1070 K
品牌: INTEL [ INTEL ]
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LXT351 T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation  
Table 22. DC Electrical Characteristics  
Parameter  
Sym  
Min  
Typ1  
Max  
Unit  
Test Conditions  
Digital I/O pins  
High level input voltage 2 (pins 1-5, 9-12, 17, 23-28)3  
Low level input voltage 2 (pins 1-5, 9-12, 17, 23-28)3  
High level output voltage 2 (pins 6-8, 10, 11,23, 28)3  
Low level output voltage 2 (pins 6-8, 10, 11,23, 28)3  
Input leakage current  
VIH  
VIL  
2.0  
0.8  
V
V
VOH  
VOL  
ILL  
2.4  
V
IOUT = -400 µA  
0.4  
±10  
V
IOUT = 1.6 mA  
µA  
1. Typical figures are at 25° C and are for design aid only; not guaranteed and not subject to production testing.  
2. Output drivers will output CMOS logic levels into CMOS loads.  
3. Listed pins are for the PLCC package. Refer to Pin Assignments and Signal Descriptionson page 8 for the 44-pin QFP  
package.  
Table 23. Analog Characteristics  
Parameter  
Min  
Typ1  
Max  
Unit  
Test Conditions  
Recommended output load on TTIP/TRING  
50  
2.4  
2.7  
3.0  
3.0  
200  
3.6  
V
T1  
E1  
RL = 100 Ω  
RL = 120 Ω  
AMI output pulse amplitudes  
3.3  
V
10 Hz - 8 kHz 3  
8 kHz - 40 kHz 3  
10 Hz - 40 kHz3  
Broad Band  
0.02  
0.025  
0.025  
0.05  
UI  
UI  
UI  
UI  
Jitter added by the  
transmitter2  
@ 1024 kHz  
1.431  
Receiver sensitivity  
0
18  
dB  
Allowable consecutive zeros before LOS (T1)  
Allowable consecutive zeros before LOS (E1)  
160  
175  
32  
190  
10 kHz - 100 kHz  
0.4  
138  
0.2  
37  
UI  
UI  
UI  
UI  
Hz  
0 dB line  
AT&T Pub 62411  
Input jitter tolerance (T1)  
1 Hz3  
10 kHz - 100 kHz  
1 Hz3  
0 dB line  
ITU (G.823)  
Input jitter tolerance (E1)  
Jitter attenuation curve corner frequency 4  
3
selectable in data port  
RTIP to RRING  
Driver output impedance  
3
Receiver input impedance  
40  
22  
28  
30  
kΩ  
dB  
dB  
dB  
51 kHz - 102 kHz3  
20  
20  
25  
Receive return loss (E1)  
102 kHz - 2.048 MHz3  
2.048 MHz - 3.072 MHz3  
1. Typical figures are at 25° C and are for design aid only; not guaranteed and not subject to production testing.  
2. Input signal to TCLK is jitter-free. The Jitter Attenuator is in the receive path or disabled.  
3. Guaranteed by characterization; not subject to production testing.  
4. Circuit attenuates jitter at 20 dB/decade above the corner frequency.  
34  
Datasheet