LXT351 — T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation
Figure 16. Intel Address/Data Bus Timing
0ns
50ns
100ns
150ns
200ns
TCLWL
TCLRL
TWHCH
TRHCH
CS
TLLRL
TLLWL
TLHLL
TLLAX
TRHLH
TWHLH
ALE
RD
TAVLL
TRLRH
TRHAV
TRHDX
TRLDV
AD0-7_R
TWLWH
TDVWH
TWHDX
WR
AD0-7_W
Table 31. 16.78 MHz Motorola Bus Parallel I/O Timing Characteristics (See Figure 17)
Parameter
Sym
Min
Max
Unit
Test Conditions
DS rising edge to AS rising edge
AS High pulse width
TDSHASH
TASHASL
TAVASL
15
35
10
10
20
10
95
10
5
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address valid setup time at AS falling edge
AS falling edge to Address valid hold time
AS falling edge to DS falling edge
CS falling edge to DS falling edge
DS Low pulse width
–
Taslax
–
TASLDSL
TCSLDSL
TDSLDSH
TDSLDV
TDSHDX
TRWLDSL
TDVDSH
Tdxdsh
TDSHRWH
TDSHCSH
–
–
–
DS falling edge to data valid
55
35
–
Data hold time after DS rising edge
R/W falling edge to DS falling edge
Data setup time before DS rising edge
Data hold time after DS rising edge
R/W Low hold time after DS rising edge
CS Low hold time after DS rising edge
10
40
30
15
15
–
–
–
–
40
Datasheet
INTEL [ INTEL ]
