T1/E1 Short Haul Transceiver with Crystal-less Jitter Attenuation — LXT351
Table 30. 20 MHz Intel Bus Parallel I/O Timing Characteristics (See Figure 16)
Parameter
Sym
Min
Max
Unit
Test Conditions
ALE pulse width
TLHLL
TAVLL
35
10
10
10
10
10
10
95
10
5
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address valid to ALE falling edge
ALE falling edge to address hold time
ALE falling edge to RD falling edge
ALE falling edge to WR falling edge
CS falling edge to RD falling edge
CS falling edge to WR falling edge
RD Low pulse width
TLLAX
TLLRL
–
–
TLLWL
TCLRL
TCLWL
TRLRH
TRLDV
TRHDX
TRHLH
TRHAV
TRHCH
TWLWH
TDVWH
TWHDX
TWHLH
TWHCH
–
–
–
–
RD falling edge to data valid
55
35
–
Data hold time after RD rising edge
RD rising edge to ALE rising edge
RD rising edge to address valid
CS Low hold time after RD rising edge
WR Low pulse width
15
35
0
–
–
95
40
30
15
15
–
Data setup time before WR rising edge
Data hold time after WR rising edge
WR rising edge to ALE rising edge
CS Low hold time after WR rising edge
–
–
–
–
Datasheet
39
INTEL [ INTEL ]
