1-Gbit P30 Family
Figure 43.
BEFP Flowchart
BUFFERED ENHANCED FACTORY PROGRAMMING (BEFP) PROCEDURE
Setup Phase
Program & Verify Phase
Exit Phase
Read
Status Reg.
Read
Status Reg.
Start
VPP applied
Block Unlocked
No (SR[7]=0)
BEFP
Exited?
No (SR[0]=1)
Data Stream
Ready?
Yes (SR[0]=0)
Yes (SR[7]=1)
Write 80h @
1st Word Address
Initialize Count:
X = 0
Full Status Check
Procedure
Write D0h @
1st Word Address
Write Data @ 1st
Word Address
Program
Complete
BEFP Setup delay
Increment Count:
X = X+1
Read
Status Reg.
N
Check
X = 32?
Yes (SR[7]=0)
Y
BEFP Setup
Done?
Read
No (SR[7]=1)
Status Reg.
No (SR[0]=1)
Check VPP, Lock
errors (SR[3,1])
Program
Done?
Yes (SR[0]=0)
Exit
N
Last
Data?
Y
Write 0xFFFF,
Address Not within
Current Block
BEFP Setup
BEFP Program & Verify
BEFP Exit
Operation Comments
Bus
State
Bus
State
Bus
State
Operation
Comments
Operation
Comments
Unlock
Block
Status
Register
Data = Status Register Data
Address = 1st Word Addr.
Status
Register
Data = Status Register Data
Address = 1st Word Addr.
Read
Write
VPPH applied to VPP
Read
Write
(Note 1)
BEFP
Setup
Data = 0x80 @ 1st Word
Address
Data = 0x80 @ 1st Word
Address1
Check SR[0]:
0 = Ready for Data
1 = Not Ready for Data
Check
Exit
Status
Check SR[7]:
0 = Exit Not Completed
1 = Exit Completed
Data Stream
Ready?
Standby
Standby
Standby
BEFP
Confirm
Write
Read
Initialize
Count
Repeat for subsequent blocks ;
X = 0
Status
Register
Data = Status Register Data
Address = 1st Word Addr.
After BEFP exit, a full Status Register check can
determine if any program error occurred;
Write
(note 2)
Load
Buffer
Data = Data to Program
Address = 1st Word Addr.
BEFP
Setup
Done?
Check SR[7]:
0 = BEFP Ready
1 = BEFP Not Ready
Standby
Increment
Count
See full Status Register check procedure in the
Word Program flowchart.
Standby
Standby
Read
X = X+1
X = 32?
Yes = Read SR[0]
No = Load Next Data Word
Error
If SR[7] is set, check:
SR[3] set = VPP Error
SR[1] set = Locked Block
Buffer
Full?
Write 0xFF to enter Read Array state.
Standby Condition
Check
Status
Register
Data = Status Reg. Data
Address = 1st Word Addr.
Check SR[0]:
0 = Program Done
1 = Program in Progress
Program
Done?
Standby
Last
Data?
No = Fill buffer again
Yes = Exit
Standby
Write
Exit Prog & Data = 0xFFFF @ address
Verify Phase not in current block
NOTES:
1. First-word address to be programmed within the target block must be aligned on a write -buffer boundary.
2. Write-buffer contents are programmed sequentially to the flash array starting at the first word address (WSM internally increments addressing).
April 2005
88
Intel StrataFlash® Embedded Memory (P30)
Order Number: 306666, Revision: 001
Datasheet
INTEL [ INTEL ]
