1-Gbit P30 Family
Figure 44.
Block Erase Flowchart
BLOCK ERASE PROCEDURE
Bus
Start
Command
Operation
Comments
Block
Erase
Setup
Data = 0x20
Addr = Block to be erased (BA)
Write
Write
Read
Write 0x20,
(Block Erase)
Block Address
Erase Data = 0xD0
Confirm Addr = Block to be erased (BA)
Write 0xD0,
(Erase Confirm)
Block Address
None
None
Status Register data.
Suspend
Erase
Loop
Read Status
Register
Check SR[7]:
1 = WSM ready
0 = WSM busy
Idle
No
Suspend
Erase
0
Yes
SR[7] =
1
Repeat for subsequent block erasures.
Full Status register check can be done after each block erase
or after a sequence of block erasures.
Full Erase
Status Check
(if desired)
Write 0xFF after the last operation to enter read array mode.
Block Erase
Complete
FULL ERASE STATUS CHECK PROCEDURE
Read Status
Register
Bus
Command
Operation
Comments
Check SR[3]:
1 = VPP Range Error
Idle
Idle
None
None
1
VPP Range
Error
SR[3] =
0
Check SR[4,5]:
Both 1 = Command Sequence Error
1,1
1
Command
Sequence Error
Check SR[5]:
1 = Block Erase Error
SR[4,5] =
0
Idle
Idle
None
None
Check SR[1]:
1 = Attempted erase of locked block;
erase aborted.
Block Erase
Error
SR[5] =
0
Only the Clear Status Register command clears SR[1, 3, 4, 5].
If an error is detected, clear the Status register before
attempting an erase retry or other error recovery.
1
Block Locked
Error
SR[1] =
0
Block Erase
Successful
Datasheet
Intel StrataFlash® Embedded Memory (P30)
Order Number: 306666, Revision: 001
April 2005
89
INTEL [ INTEL ]
