1-Gbit P30 Family
Figure 29.
Example Latency Count Setting using Code 3
tData
0
1
2
3
4
CLK
CE#
ADV#
Address
A[MAX:0]
D[15:0]
Code 3
High-Z
Data
R103
10.3.3
WAIT Polarity
The WAIT Polarity bit (WP), RCR[10] determines the asserted level (VOH or VOL) of WAIT.
When WP is set, WAIT is asserted high (default). When WP is cleared, WAIT is asserted low.
WAIT changes state on valid clock edges during active bus cycles (CE# asserted, OE# asserted,
RST# deasserted).
10.3.3.1
WAIT Signal Function
The WAIT signal indicates data valid when the device is operating in synchronous mode
(RCR[15]=0). The WAIT signal is only “deasserted” when data is valid on the bus.
When the device is operating in synchronous non-array read mode, such as read status, read ID, or
read query. The WAIT signal is also “deasserted” when data is valid on the bus.
WAIT behavior during synchronous non-array reads at the end of word line works correctly only
on the first data access.
When the device is operating in asynchronous page mode, asynchronous single word read mode,
and all write operations, WAIT is set to a deasserted state as determined by RCR[10]. See Figure
17, “Asynchronous Single-Word Read (ADV# Latch)” on page 38, and Figure 18, “Asynchronous
Page-Mode Read Timing” on page 39.
Datasheet
Intel StrataFlash® Embedded Memory (P30)
Order Number: 306666, Revision: 001
April 2005
57
INTEL [ INTEL ]
