Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
5.5.2.4
MII
Figure 20.
MII Output Timings
T
T
2
1
eth_tx_clk
eth_tx_data[7:0]
eth_tx_en
eth_crs
A9580-01
Table 48.
MII Output Timings Values
Symbol
Parameter
Min.
Max.
Units
Notes
Clock to output delay for ETH_TXDATA and
ETH_TXEN.
T1
0
2
17
ns
1
ETH_TXDATA and ETH_TXEN hold time after
ETH_TXCLK.
T2
ns
Note:
1.
These values satisfy the MII specification requirement of 0 ns to 25 ns clock to output delay.
Figure 21.
MII Input Timings
T
T
4
3
eth_rx_clk
eth_rx_data[7:0]
eth_rx_dv
eth_crs
A9581-01
Table 49.
MII Input Timings Values
Symbol
Parameter
Min.
Max.
Units
Notes
ETH_RXDATA and ETH_RXDV setup time prior
to rising edge of ETH_RXCLK
T3
5.5
ns
1, 2
ETH_RXDATA and ETH_RXDV hold time after
the rising edge of ETH_RXCLK
T4
0
ns
1, 2, 3
Notes:
1.
2.
3.
These values satisfy the MII specification requirement of 10-ns setup and hold time.
Timing tests were performed with a 70-pF capacitor to ground.
This parameter has been simulated but has not been fully tested.
March 2005
98
Datasheet
Document Number: 252479, Revision: 005
INTEL [ INTEL ]
