Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
5.5.2.7
Expansion Bus
Figure 26.
Signal Timing With Respect to Clock Rising Edge
T1
T2
T3
T4
T5
1-4 Cycles
1-4 Cycles
1-16 Cycles
1-4 Cycles
1-16 Cycles
EX_CLK
TOV
EX_CS_N[0]
EX_ADDR[23:0]
EX_IOWAIT_N
Valid Address
TOV
EX_RD_N
Thold
Tsetup
EX_DATA[15:0]
EX_WR_N
Data In
TOV
EX_DATA[15:0]
Data Out
B4870-002
Table 53.
Signal Timing With Respect to Clock Rising Edge
Symbol
Description
Min.
Max. Units
Notes
Control signal and data output valid after clock rising
edge
Tov
15
ns
Tsetup
Thold
Input Setup time with respect to clock rising edge.
Input Hold time with respect to clock rising edge.
3
2
ns
ns
1
1
Note:
1.
The Setup and Hold Timing Values are for all modes.
Datasheet
March 2005
101
Document Number: 252479, Revision: 005
INTEL [ INTEL ]
