Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
5.5.2.5
MDIO
Figure 22.
MDIO Output Timings
ETH_MDC
ETH_MDIO
T
T
1
2
A9582-02
Note: NPE is sourcing MDIO.
Figure 23.
MDIO Input Timings
T
5
ETH_MDC
ETH_MDIO
T
T
4
3
A9583-02
Note: PHY is sourcing MDIO.
Table 50.
MDIO Timings Values
Symbol
Parameter
Min.
Max.
Units
Notes
ETH_MDIO, clock to output timing with respect to
rising edge of ETH_MDC clock
ETH_MDC/2
+ 10 ns
T1
T2
T3
ns
ETH_MDIO output hold timing after the rising
edge of ETH_MDC clock
10
2
ns
ns
ETH_MDIO input setup prior to rising edge of
ETH_MDC clock
ETH_MDIO hold time after the rising edge of
ETH_MDC clock
T4
T5
0
ns
ns
1
ETH_MDC clock period
125
500
Note:
1.
This parameter is guaranteed by design but has not been 100% tested.
Datasheet
March 2005
99
Document Number: 252479, Revision: 005
INTEL [ INTEL ]
