Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
5.5.2.6
SDRAM Bus
Figure 24.
SDRAM Input Timings
Table 51.
SDRAM Input Timings Values
Symbol
Parameter
Min.
Max.
Units
Notes
Input setup prior to rising edge of clock. Inputs
included in this timing are SDM_DQ[31:0] (during
a read operation).
Tsetup
1.4
ns
Input hold time after the rising edge of the clock.
Inputs included in this timing are SDM_DQ[31:0]
(during a read operation).
Thold
1.5
ns
Figure 25.
SDRAM Output Timings
Clock
Signals
Data Valid
T
T
clk2out
holdout
A9584-01
Notes
1
Table 52.
SDRAM Output Timings Values
Symbol
Parameter
Min.
Max.
Units
Rising edge of clock-to-signal output. Outputs
included in this timing are SDM_ADDR[12:0],
SDM_BA[1:0], SDM_DQM[3:0], SDM_CKE,
SDM_WE_N, SDM_CS_N[1:0], SDM_CAS_N,
SDM_RAS_N, SDM_DQ[31:0] (during a write
operation).
Tclk2out
5.5
ns
Signal output hold time after the rising edge of
the clock. Outputs included in this timing are
SDM_DQ[31:0] (during a write operation).
Tholdout
1.5
ns
1
Note:
1.
Timing test were performed with a 70-pF load to ground.
March 2005
100
Datasheet
Document Number: 252479, Revision: 005
INTEL [ INTEL ]
