Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
5.5.2.3
UTOPIA-2
Figure 18.
UTOPIA-2 Input Timings
Clock
Signals
Tsetup
Thold
A9578-01
Table 46.
UTOPIA-2 Input Timings Values
Symbol
Parameter
Min.
Max.
Units
Notes
Input setup prior to rising edge of clock. Inputs
included in this timing are UTP_IP_DATA[7:0],
UTP_IP_SOC, AND UTP_IP_FCI, and
UTP_OP_FCI.
Tsetup
8
ns
ns
Input hold time after the rising edge of the clock.
Inputs included in this timing are
UTP_IP_DATA[7:0], UTP_IP_SOC, and
UTP_IP_FCI, and UTP_OP_FCI.
Thold
1
Figure 19.
UTOPIA-2 Output Timings
Clock
Signals
Tclk2out
Tholdout
A9579-01
Table 47.
UTOPIA-2 Output Timings Values
Symbol
Parameter
Min.
Max.
Units
Notes
Rising edge of clock to signal output. Outputs
included in this timing are UTP_IP_DATA[3:0],
UTP_OP_SOC, UTP_OP_FCO, UTP_IP_FCO,
UTP_OP_DATA[7:0], and UTP_OP_ADDR[3:0].
Tclk2out
17
ns
1
Signal output hold time after the rising edge of
the clock. Outputs included in this timing are
UTP_IP_DATA[3:0], UTP_OP_SOC,
Tholdout
1
ns
1
UTP_OP_FCO, UTP_IP_FCO,
UTP_OP_DATA[7:0], and UTP_OP_ADDR[3:0].
Note:
1.
Timing was tested with a 70-pF capacitor to ground.
Datasheet
March 2005
97
Document Number: 252479, Revision: 005
INTEL [ INTEL ]
