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GWIXP425BDT 参数 Datasheet PDF下载

GWIXP425BDT图片预览
型号: GWIXP425BDT
PDF下载: 下载PDF文件 查看货源
内容描述: 网络处理器Intel㈢ IXP42X产品线和IXC1100控制平面处理器 [Intel㈢ IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor]
分类和应用:
文件页数/大小: 134 页 / 1072 K
品牌: INTEL [ INTEL ]
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Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor  
Table 54.  
Intel® Multiplexed Mode Values  
Symbol  
Parameter  
Min. Max. Units Notes  
Pulse width of EX_ALE (ADDR is valid at the rising edge of  
EX_ALE)  
Talepulse  
1
41  
Cycles  
1, 7  
Tale2addrhold Valid address hold time after from falling edge of EX_ALE  
1
1
1
4
Cycles 1, 2, 7  
Tdval2valwrt  
Twrpulse  
Write data valid prior to EX_WR_N falling edge  
Pulse width of the EX_WR_N  
Cycles  
Cycles  
Cycles  
Cycles  
ns  
3, 7  
4, 7  
5, 7  
7
1
16  
4
Tdholdafterwr Valid data after the rising edge of EX_WR_N  
1
Tale2valcs  
Trdsetup  
Trdhold  
Valid chip select after the falling edge of EX_ALE  
Data valid required before the rising edge of EX_RD_N  
Data hold required after the rising edge of EX_RD_N  
1
4
15  
0
ns  
Time needed between successive accesses on expansion  
interface.  
Trecov  
1
16  
Cycles  
6
Notes:  
1.  
2.  
3.  
4.  
5.  
6.  
The EX_ALE signal is extended from 1 to 4 cycles based on the programming of the T1 timing  
parameter. The parameter Tale2addrhold is fixed at 1 cycle.  
Setting the address phase parameter (T1) will adjust the duration that the address appears to the external  
device.  
Setting the data setup phase parameter (T2) will adjust the duration that the data appears prior to a data  
strobe (read or write) to an external device.  
Setting the data strobe phase parameter (T3) will adjust the duration that the data strobe appears (read  
or write) to an external device. Data will be available during this time as well.  
Setting the data hold strobe phase parameter (T4) will adjust the duration that the chip selects, address,  
and data (during a write) will be held.  
Setting the recovery phase parameter (T5) will adjust the duration between successive accesses on the  
expansion interface.  
7.  
8.  
One cycle is the period of the Expansion Bus clock.  
Clock to output delay for all signals will be a maximum of 15 ns for devices requiring operation in  
synchronous mode.  
9.  
Timing tests were performed with a 70-pF capacitor to ground.  
March 2005  
104  
Datasheet  
Document Number: 252479, Revision: 005