欢迎访问ic37.com |
会员登录 免费注册
发布采购

EPM3064ATC100-7N 参数 Datasheet PDF下载

EPM3064ATC100-7N图片预览
型号: EPM3064ATC100-7N
PDF下载: 下载PDF文件 查看货源
内容描述: [EE PLD, 7.5ns, 64-Cell, CMOS, PQFP100, TQFP-100]
分类和应用: 时钟输入元件可编程逻辑
文件页数/大小: 46 页 / 711 K
品牌: INTEL [ INTEL ]
 浏览型号EPM3064ATC100-7N的Datasheet PDF文件第13页浏览型号EPM3064ATC100-7N的Datasheet PDF文件第14页浏览型号EPM3064ATC100-7N的Datasheet PDF文件第15页浏览型号EPM3064ATC100-7N的Datasheet PDF文件第16页浏览型号EPM3064ATC100-7N的Datasheet PDF文件第18页浏览型号EPM3064ATC100-7N的Datasheet PDF文件第19页浏览型号EPM3064ATC100-7N的Datasheet PDF文件第20页浏览型号EPM3064ATC100-7N的Datasheet PDF文件第21页  
MAX 3000A Programmable Logic Device Family Data Sheet  
MAX 3000A devices can be programmed on Windows–based PCs with an  
Altera Logic Programmer card, MPU, and the appropriate device adapter.  
The MPU performs continuity checking to ensure adequate electrical  
contact between the adapter and the device.  
Programming  
with External  
Hardware  
For more information, see the Altera Programming Hardware Data Sheet.  
f
The Altera software can use text– or waveform–format test vectors created  
with the Altera Text Editor or Waveform Editor to test the programmed  
device. For added design verification, designers can perform functional  
testing to compare the functional device behavior with the results of  
simulation.  
Data I/O, BP Microsystems, and other programming hardware  
manufacturers also provide programming support for Altera devices.  
For more information, see Programming Hardware Manufacturers.  
f
MAX 3000A devices include the JTAG BST circuitry defined by IEEE  
Std. 1149.1–1990. Table 7 describes the JTAG instructions supported by  
MAX 3000A devices. The pin-out tables found on the Altera web site  
(http://www.altera.com) or the Altera Digital Library show the location of  
the JTAG control pins for each device. If the JTAG interface is not  
required, the JTAG pins are available as user I/O pins.  
IEEE Std.  
1149.1 (JTAG)  
Boundary–Scan  
Support  
Table 7. MAX 3000A JTAG Instructions  
JTAG Instruction  
Description  
SAMPLE/PRELOAD Allows a snapshot of signals at the device pins to be captured and examined during  
normal device operation, and permits an initial data pattern output at the device pins  
EXTEST  
Allows the external circuitry and board–level interconnections to be tested by forcing a  
test pattern at the output pins and capturing test results at the input pins  
BYPASS  
Places the 1–bit bypass register between the TDIand TDOpins, which allows the BST  
data to pass synchronously through a selected device to adjacent devices during normal  
device operation  
IDCODE  
Selects the IDCODE register and places it between the TDIand TDOpins, allowing the  
IDCODE to be serially shifted out of TDO  
USERCODE  
ISP Instructions  
Selects the 32–bit USERCODE register and places it between the TDIand TDOpins,  
allowing the USERCODE value to be shifted out of TDO  
These instructions are used when programming MAX 3000A devices via the JTAG ports  
with the MasterBlaster, ByteBlasterMV, or BitBlaster cable, or when using a Jam STAPL  
file, JBC file, or SVF file via an embedded processor or test equipment  
Altera Corporation  
17  
 复制成功!