MAX 3000A Programmable Logic Device Family Data Sheet
The programming times described in Tables 4 through 6 are associated
with the worst-case method using the enhanced ISP algorithm.
Table 4. MAX 3000A tPULSE & CycleTCK Values
Device
Programming
Stand-Alone Verification
tVPULSE (s) CycleVTCK
tPPULSE (s)
CyclePTCK
EPM3032A
EPM3064A
EPM3128A
EPM3256A
EPM3512A
2.00
2.00
2.00
2.00
2.00
55,000
105,000
205,000
447,000
890,000
0.002
0.002
0.002
0.002
0.002
18,000
35,000
68,000
149,000
297,000
Tables 5 and 6 show the in-system programming and stand alone
verification times for several common test clock frequencies.
Table 5. MAX 3000A In-System Programming Times for Different Test Clock Frequencies
Device
fTCK
Units
10 MHz 5 MHz
2 MHz
1 MHz 500 kHz 200 kHz 100 kHz 50 kHz
EPM3032A
EPM3064A
EPM3128A
EPM3256A
EPM3512A
2.01
2.01
2.02
2.05
2.09
2.01
2.02
2.04
2.09
2.18
2.03
2.05
2.10
2.23
2.45
2.06
2.11
2.21
2.45
2.89
2.11
2.21
2.41
2.90
3.78
2.28
2.53
3.03
4.24
6.45
2.55
3.05
3.10
4.10
s
s
s
s
s
4.05
6.10
6.47
10.94
19.80
10.90
Table 6. MAX 3000A Stand-Alone Verification Times for Different Test Clock Frequencies
Device
fTCK
500 kHz 200 kHz 100 kHz 50 kHz
Units
10 MHz 5 MHz
2 MHz
1 MHz
EPM3032A
EPM3064A
EPM3128A
EPM3256A
EPM3512A
0.00
0.01
0.01
0.02
0.03
0.01
0.01
0.02
0.03
0.06
0.01
0.02
0.04
0.08
0.15
0.02
0.04
0.07
0.15
0.30
0.04
0.07
0.14
0.30
0.60
0.09
0.18
0.34
0.75
1.49
0.18
0.35
0.68
1.49
2.97
0.36
0.70
1.36
2.98
5.94
s
s
s
s
s
16
Altera Corporation
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