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EP4CE22E22I7N 参数 Datasheet PDF下载

EP4CE22E22I7N图片预览
型号: EP4CE22E22I7N
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 1395 CLBs, 472.5MHz, 22320-Cell, PQFP144, 22 X 22 MM, 0.50 MM PITCH, LEAD FREE, EQFP-144]
分类和应用: 时钟LTEPC可编程逻辑
文件页数/大小: 44 页 / 663 K
品牌: INTEL [ INTEL ]
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Chapter 1: Cyclone IV Device Datasheet  
Switching Characteristics  
1–29  
C9L  
Table 1–31. RSDS Transmitter Timing Specifications for Cyclone IV Devices (1), (2), (4) (Part 2 of 2)  
C6  
C7, I7  
C8, A7  
C8L, I8L  
Symbol  
Modes  
Unit  
Min Typ Max Min Typ Max Min Typ  
Max Min Typ Max Min Typ Max  
(3)  
tLOCK  
1
1
1
1
1
ms  
Notes to Table 1–31:  
(1) Applicable for true RSDS and emulated RSDS_E_3R transmitter.  
(2) Cyclone IV E devices—true RSDS transmitter is only supported at the output pin of Row I/O Banks 1, 2, 5, and 6. Emulated RSDS transmitter is supported at the  
output pin of all I/O Banks.  
Cyclone IV GX devices—true RSDS transmitter is only supported at the output pin of Row I/O Banks 5 and 6. Emulated RSDS transmitter is supported at the output  
pin of I/O Banks 3, 4, 5, 6, 7, 8, and 9.  
(3) tLOCK is the time required for the PLL to lock from the end-of-device configuration.  
(4) Cyclone IV E 1.0 V core voltage devices only support C8L, C9L, and I8L speed grades. Cyclone IV E 1.2 V core voltage devices only support C6, C7, C8, I7, and A7  
speed grades. Cyclone IV GX devices only support C6, C7, C8, and I7 speed grades.  
Table 1–32. Emulated RSDS_E_1R Transmitter Timing Specifications for Cyclone IV Devices (1), (3) (Part 1 of 2)  
C6  
C7, I7  
C8, A7  
C8L, I8L  
C9L  
Symbol  
Modes  
Unit  
Min Typ Max Min Typ Max Min Typ Max Min Typ Max Min Typ Max  
×10  
×8  
×7  
×4  
×2  
×1  
×10  
×8  
×7  
×4  
×2  
×1  
5
5
85  
85  
5
5
5
5
5
5
85  
85  
5
5
5
5
5
5
85  
85  
5
5
5
5
5
5
85  
85  
5
5
5
5
5
5
72.5 MHz  
72.5 MHz  
72.5 MHz  
72.5 MHz  
72.5 MHz  
145 MHz  
145 Mbps  
145 Mbps  
145 Mbps  
145 Mbps  
145 Mbps  
145 Mbps  
f
HSCLK (input  
5
85  
85  
85  
85  
clock  
frequency)  
5
85  
85  
85  
85  
5
85  
85  
85  
85  
5
170  
170  
170  
170  
100  
80  
70  
40  
20  
10  
45  
170 100  
170 80  
170 70  
170 40  
170 20  
170 10  
170 100  
170 80  
170 70  
170 40  
170 20  
170 10  
170 100  
170 80  
170 70  
170 40  
170 20  
170 10  
170 100  
170 80  
170 70  
170 40  
170 20  
170 10  
Device  
operation in  
Mbps  
tDUTY  
55  
45  
55  
45  
55  
45  
55  
45  
55  
%
TCCS  
200  
200  
200  
200  
200  
ps  
Output jitter  
(peak to peak)  
500  
500  
550  
600  
700  
ps  
20 – 80%,  
tRISE  
500  
500  
500  
500  
500  
ps  
CLOAD  
5 pF  
=
20 – 80%,  
tFALL  
500  
500  
500  
500  
500  
ps  
CLOAD  
5 pF  
=
March 2016 Altera Corporation  
Cyclone IV Device Handbook,  
Volume 3  
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