Chapter 1: Cyclone IV Device Datasheet
1–17
Switching Characteristics
Transceiver Performance Specifications
Table 1–21 lists the Cyclone IV GX transceiver specifications.
Table 1–21. Transceiver Specification for Cyclone IV GX Devices (Part 1 of 4)
C6
Typ
C7, I7
Typ
C8
Symbol/
Description
Conditions
Unit
Min
Max
Min
Max
Min
Typ
Max
Reference Clock
Supported I/O
Standards
1.2 V PCML, 1.5 V PCML, 3.3 V PCML, Differential LVPECL, LVDS, HCSL
Input frequency
from REFCLK input
pins
—
50
—
—
156.25
50
—
—
156.25
50
—
—
156.25
MHz
Spread-spectrum
modulating clock
frequency
Physical interface
for PCI Express
(PIPE) mode
30
—
33
—
30
—
33
—
30
—
33
—
kHz
—
Spread-spectrum
downspread
0 to
–0.5%
0 to
–0.5%
0 to
–0.5%
PIPE mode
Peak-to-peak
differential input
voltage
—
—
0.1
—
1.6
0.1
—
1100 5%
—
1.6
0.1
—
1.6
V
VICM (AC coupled)
1100 5%
—
1100 5%
—
mV
mV
HCSL I/O
standard for PCIe
reference clock
VICM (DC coupled)
250
550
250
550
250
550
Transmitter REFCLK
Phase Noise (1)
—
—
—
—
—
–123
42.3
—
—
—
—
—
—
–123
42.3
—
—
—
—
—
—
–123
42.3
—
dBc/Hz
ps
Frequency offset
= 1 MHz – 8 MHZ
Transmitter REFCLK
Total Jitter (1)
2000
1%
2000
1%
2000
1%
Rref
—
Transceiver Clock
cal_blk_clk clock
frequency
—
10
—
125
—
10
—
125
—
10
—
125
—
MHz
MHz
fixedclk clock
frequency
PCIe Receiver
Detect
—
125
—
125
—
125
Dynamic
reconfiguration
clock frequency
2.5/
2.5/
2.5/
reconfig_clk
clock frequency
37.5
—
—
50
2
37.5
—
—
50
2
37.5
—
—
50
2
MHz
ms
(2)
(2)
(2)
Delta time between
reconfig_clk
—
—
—
—
—
—
—
Transceiver block
minimum
power-down pulse
width
—
1
—
1
—
1
—
µs
March 2016 Altera Corporation
Cyclone IV Device Handbook,
Volume 3
INTEL [ INTEL ]
