EP4CE22E22I7N 参数 Datasheet PDF下载

型号：	EP4CE22E22I7N
PDF下载：	下载PDF文件查看货源
内容描述：	[Field Programmable Gate Array, 1395 CLBs, 472.5MHz, 22320-Cell, PQFP144, 22 X 22 MM, 0.50 MM PITCH, LEAD FREE, EQFP-144]
分类和应用：	时钟LTEPC栅可编程逻辑
文件页数/大小：	44 页 / 663 K
品牌：	INTEL [ INTEL ]

Chapter 1: Cyclone IV Device Datasheet

1–15

Operating Conditions

(1)

Table 1–20. Differential I/O Standard Specifications for Cyclone IV Devices

(Part 2 of 2)

(2)

(3)

V_CCIO(V)

Typ

V_ID(mV)

V_IcM(V)

V_OD(mV)

Max Min Typ Max Min

V_OS(V)

Typ

I/O Standard

Min

Max Min Max Min

Condition

Max

0.05

D_MAX 500 Mbps 1.80

LVDS

(Column

I/Os)

500 Mbps  D_MAX

 700 Mbps

2.375

2.5

2.625 100

—

0.55

1.05

—

1.80 247

1.55

—

600 1.125 1.25 1.375

_MAX> 700 Mbps

BLVDS (Row

I/Os)

2.375

2.5

2.625 100

—

(4)

BLVDS

(Column

I/Os)

—

(4)

mini-LVDS

(Row I/Os)

2.375

2.5

2.625

—

300

—

600

1.0

1.2

1.4

(5)

mini-LVDS

(Column

I/Os)

2.375

2.5

2.625

—

1.0

0.5

1.2

1.4

1.5

1.4

(5)

RSDS^®(Row

100 200 600

I/Os) ⁽⁵⁾

RSDS

(Column

I/Os)

(5)

PPDS (Row

I/Os)

(5)

PPDS

(Column

I/Os)

(5)

Notes to Table 1–20:

(1) For an explanation of terms used in Table 1–20, refer to “Glossary” on page 1–37.

(2) V_INrange: 0 V  V_IN 1.85 V.

(3) R_Lrange: 90  R_L 110  .

(4) There are no fixed V_IN, V_OD, and V_OSspecifications for BLVDS. They depend on the system topology.

(5) The Mini-LVDS, RSDS, and PPDS standards are only supported at the output pins.

(6) The LVPECL I/O standard is only supported on dedicated clock input pins. This I/O standard is not supported for output pins.

March 2016 Altera Corporation

Cyclone IV Device Handbook,

Volume 3

电子百科

产品导航

EP4CE22E22I7N 参数 Datasheet PDF下载

IC37:专业IC行业平台